eDP

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:9832KB
下载次数:83
上传日期:2013-10-23 09:01:51
上 传 者hxfcnbowen
说明:  eDP接口TFT-LCD显示驱动原码(verilog+c)
(eDP Interface TFT-LCD display driver source code (verilog+c))

文件列表:
eDP_51_final_2013.6.5\DP_501.opt.bak (4624, 2013-04-09)
eDP_51_final_2013.6.5\DP_501.plg (149, 2013-01-03)
eDP_51_final_2013.6.5\DP_501.Uv2.bak (2012, 2013-04-09)
eDP_51_final_2013.6.5\DP_501.uvgui.Administrator (137112, 2013-06-20)
eDP_51_final_2013.6.5\DP_501.uvgui_Administrator.bak (136689, 2013-06-05)
eDP_51_final_2013.6.5\DP_501.uvopt (15205, 2013-06-20)
eDP_51_final_2013.6.5\DP_501.uvproj (14908, 2013-05-13)
eDP_51_final_2013.6.5\DP_501_Opt.Bak (4598, 2013-04-09)
eDP_51_final_2013.6.5\DP_501_Uv2.Bak (2013, 2013-03-28)
eDP_51_final_2013.6.5\DP_501_uvopt.bak (15197, 2013-06-05)
eDP_51_final_2013.6.5\DP_501_uvproj.bak (14739, 2013-04-21)
eDP_51_final_2013.6.5\INC\delay.h (153, 2013-05-12)
eDP_51_final_2013.6.5\INC\DP501.h (220, 2013-06-05)
eDP_51_final_2013.6.5\INC\DP501ADDRESS.H (8743, 2013-01-11)
eDP_51_final_2013.6.5\INC\IIC.h (1210, 2013-06-05)
eDP_51_final_2013.6.5\INC\sets.h (670, 2013-05-12)
eDP_51_final_2013.6.5\key.c (18, 2013-06-05)
eDP_51_final_2013.6.5\key.h (130, 2013-06-05)
eDP_51_final_2013.6.5\LIST\delay.lst (1529, 2013-06-20)
eDP_51_final_2013.6.5\LIST\DP501.lst (4912, 2013-06-20)
eDP_51_final_2013.6.5\LIST\DP_501.m51 (30654, 2013-06-20)
eDP_51_final_2013.6.5\LIST\IIC.lst (12389, 2013-06-20)
eDP_51_final_2013.6.5\LIST\key.lst (829, 2013-06-20)
eDP_51_final_2013.6.5\LIST\main.lst (2171, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\delay.obj (1415, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\DP501.obj (27061, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\DP_501 (70448, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\DP_501.hex (5458, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\DP_501.lnp (157, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\DP_501.plg (2224, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\IIC.obj (22624, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\key.obj (2135, 2013-06-20)
eDP_51_final_2013.6.5\OBJ\main.obj (23239, 2013-06-20)
eDP_51_final_2013.6.5\SRC\delay.c (359, 2013-06-05)
eDP_51_final_2013.6.5\SRC\DP501.c (2168, 2013-06-05)
eDP_51_final_2013.6.5\SRC\IIC.c (5188, 2013-06-20)
eDP_51_final_2013.6.5\SRC\main.c (603, 2013-06-05)
eDP_FPGA_13.3_2013.6.5\.qsys_edit\filters.xml (69, 2013-05-02)
eDP_FPGA_13.3_2013.6.5\.qsys_edit\preferences.xml (534, 2013-05-02)
eDP_FPGA_13.3_2013.6.5\altlvds_tx0.bsf (2092, 2012-11-25)
... ...

This folder contains data for incremental compilation. The compiled_partitions sub-folder contains previous compilation results for each partition. As long as this folder is preserved, incremental compilation results from earlier compiles can be re-used. To perform a clean compilation from source files for all partitions, both the db and incremental_db folder should be removed. The imported_partitions sub-folder contains the last imported QXP for each imported partition. As long as this folder is preserved, imported partitions will be automatically re-imported when the db or incremental_db/compiled_partitions folders are removed.

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