FPGA_TENNIS
所属分类：VHDL/FPGA/Verilog
开发工具：TEXT
文件大小：304KB
下载次数：100
上传日期：2006-12-31 10:39:10
上 传 者：
jsjtcl
说明： 基于FPGA的乒乓球游戏硬件电路的设计与实现，有完整的VHDL代码，并有PDF详细说明如何下载及跳线设置，并在GW48系列开发平台上下载调试成功
(FPGA-based table tennis game hardware circuit design and realization of a complete VHDL code. and a detailed account of how the PDF download and jumper settings and in a series of development platforms GW48 download debugging success!)
文件列表:
实验10_2.pdf (316810, 2005-08-10)
EP1C3_10_2_TENNIS\BALL.VHD (807, 1999-11-09)
EP1C3_10_2_TENNIS\BALLCTRL.VHD (1239, 1999-11-18)
EP1C3_10_2_TENNIS\BOARD.VHD (913, 1999-11-18)
EP1C3_10_2_TENNIS\cmp_state.ini (3, 2005-08-02)
EP1C3_10_2_TENNIS\COU10.VHD (574, 1999-11-18)
EP1C3_10_2_TENNIS\COU4.VHD (575, 1999-11-18)
EP1C3_10_2_TENNIS\MWAY.VHD (443, 1999-11-09)
EP1C3_10_2_TENNIS\SOUND.VHD (347, 1999-11-18)
EP1C3_10_2_TENNIS\TENNIS.asm.rpt (9225, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.CDF (329, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.done (26, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.fit.eqn (18537, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.fit.rpt (76613, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.fit.summary (383, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.flow.rpt (4074, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.map.eqn (14844, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.map.rpt (25127, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.map.summary (323, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.PIN (19980, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.QPF (1559, 2005-08-02)
EP1C3_10_2_TENNIS\TENNIS.QSF (4436, 2005-08-02)
EP1C3_10_2_TENNIS\TENNIS.QWS (246, 2005-08-02)
EP1C3_10_2_TENNIS\TENNIS.SOF (74078, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.tan.rpt (73712, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.tan.summary (2773, 2005-05-10)
EP1C3_10_2_TENNIS\TENNIS.VHD (1918, 2001-06-21)
EP1C3_10_2_TENNIS (0, 2006-12-20)
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