文件列表:

ddr3_mcb1\custom_part\ddr3_sdram\components\mt41j128m16jt-125.xml (12880, 2013-10-30)
ddr3_mcb1\custom_part\user_parts.xml (323, 2013-10-30)
ddr3_mcb1\ddr3_mcb1.cgc (68385, 2013-10-30)
ddr3_mcb1\ddr3_mcb1.cgp (523, 2013-10-30)
ddr3_mcb1\mig_37\docs\ug388.pdf (2172724, 2010-10-06)
ddr3_mcb1\mig_37\docs\ug416.pdf (7337767, 2010-10-06)
ddr3_mcb1\mig_37\example_design\datasheet.txt (2379, 2013-10-30)
ddr3_mcb1\mig_37\example_design\log.txt (2370, 2013-10-30)
ddr3_mcb1\mig_37\example_design\mig.prj (3128, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\coregen.cgc (63720, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\coregen.cgp (518, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\coregen.log (1649, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\create_ise.bat (3265, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.bgn (8660, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.bit (2453207, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.bld (69871, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.cdc (13980, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.cmd_log (1624, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.drc (2375, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ncd (996242, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ngc (1619737, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ngd (2921388, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ngr (2380029, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.pad (27832, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.par (32404, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.pcf (479440, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.prj (1260, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ptwx (23183, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.stx (0, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.syr (517267, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.twr (259678, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.twx (297575, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ucf (10637, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.unroutes (1025, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.ut (567, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.xpi (46, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top.xst (1173, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top_bitgen.xwbt (334, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top_envsettings.html (14638, 2013-10-30)
ddr3_mcb1\mig_37\example_design\par\example_top_guide.ncd (996242, 2013-10-30)
... ...

The design files are located at E:/_hardriver/fpga: - mig_37.veo: veo template file containing code that can be used as a model for instantiating a CORE Generator module in a HDL design. - mig_37.xco: CORE Generator input file containing the parameters used to regenerate a core. - mig_37_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. - mig_37_readme.txt: Text file indicating the files generated and how they are used. - mig_37_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. - mig_37 directory. In the mig_37 directory, three folders are created: - docs: This folder contains user guide. - example_design: This folder includes the design with synthesizable test bench. - user_design: This folder includes the design without test bench modules. The example_design and user_design folders contain several other folders and files. All these output folders are discussed in more detail in Spartan-6 FPGA Memory Controller user guide (ug388.pdf) located in docs folder.

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