simple_spi_latest.tar
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：562KB
下载次数：20
上传日期：2013-11-13 15:16:39
上 传 者：
lanyuewangzi
说明： spi master spi master spi master spi master
(spi read and write spi master spi master spi master)
文件列表:
simple_spi (0, 2013-11-11)
simple_spi\tags (0, 2013-11-11)
simple_spi\tags\initial (0, 2013-11-11)
simple_spi\tags\initial\rtl (0, 2013-11-11)
simple_spi\tags\initial\rtl\verilog (0, 2013-11-11)
simple_spi\tags\initial\rtl\verilog\fifo4.v (4290, 2002-12-23)
simple_spi\tags\initial\rtl\verilog\simple_spi_top.v (9873, 2002-12-23)
simple_spi\branches (0, 2013-11-11)
simple_spi\trunk (0, 2013-11-11)
simple_spi\trunk\doc (0, 2013-11-11)
simple_spi\trunk\doc\simple_spi.pdf (55328, 2003-01-07)
simple_spi\trunk\doc\src (0, 2013-11-11)
simple_spi\trunk\doc\src\simple_spi.doc (400896, 2003-01-07)
simple_spi\trunk\sim (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\run (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\run\simvision.sv (15216, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\run\ncwork\hdl.var (1076, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work\.inca.db.148.lnx86 (0, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work\.cdsvmod (0, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work\inca.linux.135.pak (1260491, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work\inca.lnx86.148.pak (1485485, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\work\.inca.db.135.linux (0, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncwork\cds.lib (57, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\waves (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\run\waves\waves.do (5215, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\stdout.log (0, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncsim.log (255, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\ncvlog.log (78, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\run\Makefile (3510, 2004-02-29)
simple_spi\trunk\sim\rtl_sim\bin (0, 2013-11-11)
simple_spi\trunk\sim\rtl_sim\bin\Makefile (3510, 2004-02-29)
simple_spi\trunk\bench (0, 2013-11-11)
simple_spi\trunk\bench\verilog (0, 2013-11-11)
simple_spi\trunk\bench\verilog\wb_master_model.v (5512, 2004-02-29)
simple_spi\trunk\bench\verilog\spi_slave_model.v (3773, 2004-02-29)
simple_spi\trunk\bench\verilog\tst_bench_top.v (6264, 2004-02-29)
simple_spi\trunk\rtl (0, 2013-11-11)
... ...
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