verilog_multiplier
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：25KB
下载次数：435
上传日期：2007-01-06 21:52:04
上 传 者：
zzmfreeman
说明： verilog实现16*16位乘法器，带测试文件
(verilog achieve 16* 16 multiplier, with test documents)
文件列表:
multiplier\coregen\coregen.cgp (616, 2006-12-04)
multiplier\coregen\multi_16x16.edn (357310, 2006-12-04)
multiplier\coregen\multi_16x16.v (3995, 2006-12-04)
multiplier\coregen\multi_16x16.veo (2987, 2006-12-04)
multiplier\coregen\multi_16x16.xco (1589, 2006-12-04)
multiplier\coregen\multi_16x16_flist.txt (131, 2006-12-04)
multiplier\coregen\tmp\_cg (0, 2006-12-04)
multiplier\coregen\tmp (0, 2006-12-04)
multiplier\coregen (0, 2006-12-04)
multiplier (0, 2006-12-04)
The following files were generated for in directory
D:\My_Designs\example\class7\multiplier\coregen\:
multi_16x16.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
multi_16x16.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
multi_16x16.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
multi_16x16.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
multi_16x16_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
multi_16x16_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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