文件列表:

Design Example\db (0, 2008-04-29)
Design Example\db\altfp_mult_g5v.tdf (25188, 2008-04-28)
Design Example\db\fp_mult_ex.(0).cnf.cdb (3341, 2008-04-28)
Design Example\db\fp_mult_ex.(0).cnf.hdb (1562, 2008-04-28)
Design Example\db\fp_mult_ex.(1).cnf.cdb (2764, 2008-04-28)
Design Example\db\fp_mult_ex.(1).cnf.hdb (598, 2008-04-28)
Design Example\db\fp_mult_ex.(2).cnf.cdb (25306, 2008-04-28)
Design Example\db\fp_mult_ex.(2).cnf.hdb (5970, 2008-04-28)
Design Example\db\fp_mult_ex.(3).cnf.cdb (13682, 2008-04-28)
Design Example\db\fp_mult_ex.(3).cnf.hdb (3792, 2008-04-28)
Design Example\db\fp_mult_ex.asm.qmsg (2212, 2008-04-28)
Design Example\db\fp_mult_ex.asm_labs.ddb (37371, 2008-04-28)
Design Example\db\fp_mult_ex.cbx.xml (208, 2008-04-29)
Design Example\db\fp_mult_ex.cmp.bpm (1986, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.cdb (152358, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.ecobp (28, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.hdb (32193, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.logdb (87877, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.rdb (48953, 2008-04-28)
Design Example\db\fp_mult_ex.cmp.tdb (523313, 2008-04-28)
Design Example\db\fp_mult_ex.cmp0.ddb (501464, 2008-04-28)
Design Example\db\fp_mult_ex.db_info (146, 2008-04-28)
Design Example\db\fp_mult_ex.eco.cdb (170, 2008-04-29)
Design Example\db\fp_mult_ex.eda.qmsg (2415, 2008-04-28)
Design Example\db\fp_mult_ex.eds_overflow (3, 2008-04-29)
Design Example\db\fp_mult_ex.fit.qmsg (242347, 2008-04-28)
Design Example\db\fp_mult_ex.fnsim.cdb (29109, 2008-04-29)
Design Example\db\fp_mult_ex.fnsim.hdb (36739, 2008-04-29)
Design Example\db\fp_mult_ex.fnsim.qmsg (7295, 2008-04-29)
Design Example\db\fp_mult_ex.hier_info (94995, 2008-04-29)
Design Example\db\fp_mult_ex.hif (9093, 2008-04-28)
Design Example\db\fp_mult_ex.map.bpm (1973, 2008-04-28)
Design Example\db\fp_mult_ex.map.cdb (28352, 2008-04-28)
Design Example\db\fp_mult_ex.map.ecobp (28, 2008-04-28)
Design Example\db\fp_mult_ex.map.hdb (29509, 2008-04-28)
Design Example\db\fp_mult_ex.map.logdb (567, 2008-04-28)
Design Example\db\fp_mult_ex.map.qmsg (9497, 2008-04-28)
Design Example\db\fp_mult_ex.map_bb.cdb (1526, 2008-04-28)
Design Example\db\fp_mult_ex.map_bb.hdb (6567, 2008-04-28)
Design Example\db\fp_mult_ex.map_bb.hdbx (7890, 2008-04-28)
... ...

====================================================================================================== This is a readme.txt file for the Floating Point Multiplier (ALTFP_MULT) Megafunction design example ====================================================================================================== This readme.txt file shows the list of files in the design example you downloaded. For more instructions or information on the design examples, refer to the Megafunction User Guide. Although we have made every effort to ensure that this design example compiles correctly in the Quartus(R) II software, there may be problems that we have not encountered. For further assistance, please contact Altera Technical Support by filing a service request at http://mysupport.altera.com. The design example contains a different set of files for the Quartus II and ModelSim-Altera software respectively. FILES IN DESIGN EXAMPLE (QUARTUS II SOFTWARE) ============================================= The design example for the Quartus II software contains the following file: FILE TYPE DESCRIPTION ========= =========== *.qar The Quartus Archive File (.qar) is a compressed file that contains a project and its related files. Files that are related to a project include design files, the Quartus II Project File (.qpf), the Quartus II Settings File (.qsf), the Quartus II Defaults File (.qdf), and the archive activity log (.qarlog). FILES IN DESIGN EXAMPLE (MODELSIM-ALTERA) ========================================= The design example for the ModelSim-Altera software contains the following files: FILE TYPE DESCRIPTION ========= =========== *.vo Verilog Hardware Description Language (HDL) standard netlist file that is generated by the Quartus II Compiler. *.vho Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) standard netlist file that is generated by the Quartus II Compiler. *.vt ASCII text file that is generated by the Quartus II software, or with the Quartus II Text Editor or other standard text editors. Contains an instantiation of the top-level design entity for a design, and simulation input vectors and simulation output vectors. Verilog Test Bench Files are used for simulation of a design with other EDA tools. *.vht VHDL Test Bench File. Contains an instantiation of a design entity, usually the top-level design entity, and code to create simulation input vectors and to test the behavior of simulation output vectors. VHDL Test Bench files are used with an EDA simulation tool to test the behavior of an HDL design entity. *.do ModelSim macros (also called DO files) are scripts that contain ModelSim and, optionally, Tcl commands. You can invoke these scripts with the Tools > Execute Macro command or the do command. *.sdo Output file generated by the Quartus II Compiler. The Standard Delay Format is an industry-standard format. Contains timing-delay information that allows you to perform the following tasks: - back-annotation for simulation in VHDL simulators with simulation libraries that are compliant with VITAL version 2.2b and version 3.0 (VITAL 95) - back-annotation for simulation in Verilog HDL simulators - timing analysis and physical synthesis with EDIF simulation and synthesis tools SDF output files that are generated for EDA simulation tools do not contain negative set-up and hold times.

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