hdb3_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：22KB
下载次数：135
上传日期：2007-01-18 12:28:03
上 传 者：
chengroc
说明： modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench
(modelsim works with verilog realized HDB3 coding, and testing procedures testbench)
文件列表:
hdb3\decode.v (1860, 2007-01-18)
hdb3\testbench.v (939, 2007-01-17)
hdb3\testbench.v.bak (939, 2007-01-17)
hdb3\work\_info (468, 2007-01-18)
hdb3\work\testbench\_primary.vhd (78, 2007-01-18)
hdb3\work\testbench\verilog.asm (7458, 2007-01-18)
hdb3\work\testbench\_primary.dat (910, 2007-01-18)
hdb3\work\testbench (0, 2007-01-18)
hdb3\work\decode\_primary.vhd (341, 2007-01-18)
hdb3\work\decode\verilog.asm (11305, 2007-01-18)
hdb3\work\decode\_primary.dat (1671, 2007-01-18)
hdb3\work\decode (0, 2007-01-18)
hdb3\work (0, 2007-01-18)
hdb3\decode.v.bak (1948, 2007-01-17)
hdb3\hdb3.cr.mti (244, 2007-01-18)
hdb3\hdb3.mpf (20671, 2007-01-18)
hdb3 (0, 2007-01-18)
hdb3\vsim.wlf (32768, 2007-01-18)
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