jpeg_encoder
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：175KB
下载次数：13
上传日期：2013-12-27 17:30:25
上 传 者：
czwko
说明： JPEG 编码器IP核，用verilog语言编写，不支持二级采样。
(JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling)
文件列表:
jpeg_encoder\cbd_q_h.v (8614, 2009-11-17)
jpeg_encoder\cb_dct.v (34232, 2009-11-17)
jpeg_encoder\cb_huff.v (72951, 2009-11-17)
jpeg_encoder\cb_quantizer.v (32737, 2009-11-17)
jpeg_encoder\crd_q_h.v (8615, 2009-11-17)
jpeg_encoder\cr_dct.v (34232, 2009-11-17)
jpeg_encoder\cr_huff.v (72947, 2009-11-17)
jpeg_encoder\cr_quantizer.v (32732, 2009-11-17)
jpeg_encoder\document\JPEG Encoder.doc (38912, 2009-11-21)
jpeg_encoder\ff_checker.v (21156, 2009-11-17)
jpeg_encoder\fifo_out.v (26022, 2010-02-15)
jpeg_encoder\ja.jpg (9101, 2009-11-17)
jpeg_encoder\ja.tif (27906, 2009-11-17)
jpeg_encoder\ja_bits_out.v (21187, 2009-11-17)
jpeg_encoder\jpeg_top.v (3842, 2009-11-17)
jpeg_encoder\jpeg_top_TB.v (481168, 2010-02-15)
jpeg_encoder\jpeg_top_TB_runtest.do (1151, 2009-11-17)
jpeg_encoder\pre_fifo.v (3876, 2009-11-17)
jpeg_encoder\rgb2ycbcr.v (5184, 2009-11-17)
jpeg_encoder\sync_fifo_32.v (3587, 2009-11-17)
jpeg_encoder\sync_fifo_ff.v (4500, 2009-11-17)
jpeg_encoder\yd_q_h.v (8639, 2009-11-17)
jpeg_encoder\y_dct.v (33796, 2009-11-17)
jpeg_encoder\y_huff.v (70296, 2009-11-17)
jpeg_encoder\y_quantizer.v (32730, 2009-11-17)
jpeg_encoder\document (0, 2013-12-27)
jpeg_encoder (0, 2013-12-27)
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