exp6_Uart
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：633KB
下载次数：4
上传日期：2013-12-27 21:29:16
上 传 者：
zhumj1991
说明： xilinx FPGA的rs232 Verilog HDL程序
(xilinx FPGA的rs232 Verilog HDL)
文件列表:
exp6_Uart\Analysis 2.twx (19076, 2011-09-27)
exp6_Uart\baud_gen.v (982, 2008-10-20)
exp6_Uart\baud_gen_summary.html (3176, 2008-10-20)
exp6_Uart\baud_gen_xst.xrpt (4736, 2008-10-20)
exp6_Uart\coregen_xil_944_84.cgc (2071, 2011-09-22)
exp6_Uart\coregen_xil_944_84.cgp (518, 2011-09-22)
exp6_Uart\cs_uart.cdc (5449, 2010-07-16)
exp6_Uart\cs_uart.cpj (24299, 2008-11-11)
exp6_Uart\device_usage_statistics.html (66626, 2010-07-16)
exp6_Uart\fuse.log (1106, 2008-11-02)
exp6_Uart\iseconfig\uart.projectmgr (6220, 2012-05-06)
exp6_Uart\iseconfig\uart_top.xreport (11681, 2012-05-06)
exp6_Uart\isim.cmd (14, 2008-11-02)
exp6_Uart\isim.hdlsourcefiles (144, 2008-11-02)
exp6_Uart\isim.log (1027, 2008-11-02)
exp6_Uart\isimwavedata.xwv (39752, 2008-11-02)
exp6_Uart\par_usage_statistics.html (4137, 2011-09-14)
exp6_Uart\tb_buad_gen.v (998, 2008-11-02)
exp6_Uart\tb_buad_gen_beh.prj (111, 2008-11-02)
exp6_Uart\tb_buad_gen_isim_beh.exe (17233, 2008-11-02)
exp6_Uart\tb_buad_gen_isim_beh.wfs (654, 2008-11-02)
exp6_Uart\tb_buad_gen_stx.prj (126, 2008-11-02)
exp6_Uart\tb_uart_rx.v (1120, 2008-10-21)
exp6_Uart\tb_uart_rx_isim_beh.wfs (996, 2008-10-21)
exp6_Uart\tb_uart_rx_stx.prj (124, 2008-10-21)
exp6_Uart\tb_uart_tx.v (1583, 2008-10-20)
exp6_Uart\tb_uart_tx2.v (1184, 2008-10-21)
exp6_Uart\tb_uart_tx2_beh.prj (110, 2008-10-21)
exp6_Uart\tb_uart_tx2_isim_beh.exe (17233, 2008-10-21)
exp6_Uart\tb_uart_tx2_isim_beh.wfs (855, 2008-10-21)
exp6_Uart\tb_uart_tx2_stx.prj (125, 2008-10-21)
exp6_Uart\tb_uart_tx_isim_beh.wfs (912, 2008-10-20)
exp6_Uart\tb_uart_tx_stx.prj (124, 2008-10-20)
exp6_Uart\uart.gise (1055, 2012-05-06)
exp6_Uart\uart.ntrc_log (3473, 2010-07-16)
exp6_Uart\uart.restore (58992, 2010-08-28)
exp6_Uart\uart.xise (50512, 2012-05-06)
exp6_Uart\uart_cs.cdc (2607, 2008-10-21)
exp6_Uart\uart_rx.v (2695, 2008-11-02)
exp6_Uart\uart_rx_summary.html (3175, 2008-10-21)
... ...
The following files were generated for 'icon_pro' in directory
E:\PX\Interface\LABD1D2\LAB2\Uart\_ngo\cs_icon_pro\
icon_pro.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
icon_pro.vhd:
Unisim VHDL file containing the information required to simulate
the module.
icon_pro.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
icon_pro.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
icon_pro.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro_readme.txt:
Text file indicating the files generated and how they are used.
icon_pro_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
icon_pro_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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