文件列表:

Lab4\clock_generator_0.log (418, 2012-10-09)
Lab4\data\ps7_constraints.ucf (13232, 2012-10-09)
Lab4\data\ps7_constraints.xdc (26888, 2012-10-09)
Lab4\data\ps7_system_prj.xml (9687, 2012-10-09)
Lab4\data\system.ucf (424, 2012-10-09)
Lab4\data\system.xdc (59, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\data\my_axi_ip_v2_1_0.mdd (590, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\data\my_axi_ip_v2_1_0.tcl (582, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\src\Makefile (867, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\src\my_axi_ip.c (609, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\src\my_axi_ip.h (4194, 2012-10-09)
Lab4\drivers\my_axi_ip_v1_00_a\src\my_axi_ip_selftest.c (3087, 2012-10-09)
Lab4\etc\bitgen.ut (39, 2012-10-09)
Lab4\etc\download.cmd (115, 2012-10-09)
Lab4\etc\fast_runtime.opt (2794, 2012-10-09)
Lab4\etc\system.filters (8592, 2012-10-09)
Lab4\etc\system.gui (13246, 2012-10-09)
Lab4\hdl\system.vhd (85509, 2012-10-09)
Lab4\hdl\system_axi_interconnect_1_wrapper.v (36411, 2012-10-09)
Lab4\hdl\system_my_axi_ip_0_wrapper.vhd (3991, 2012-10-09)
Lab4\hdl\system_processing_system7_0_wrapper.v (74322, 2012-10-09)
Lab4\hdl\system_stub.vhd (4760, 2012-10-09)
Lab4\implementation\axi_interconnect_1_wrapper\axi_interconnect_1.xdc (875, 2012-10-09)
Lab4\implementation\axi_interconnect_1_wrapper\system_axi_interconnect_1_wrapper.ngc (269826, 2012-10-09)
Lab4\implementation\axi_interconnect_1_wrapper\_xmsgs\ngcbuild.xmsgs (367, 2012-10-09)
Lab4\implementation\bitgen.ut (39, 2012-10-09)
Lab4\implementation\cache\cache.cat (16580, 2012-10-09)
Lab4\implementation\cache\system_axi_interconnect_1_wrapper.ngc (269980, 2012-10-09)
Lab4\implementation\cache\system_my_axi_ip_0_wrapper.ngc (44407, 2012-10-09)
Lab4\implementation\cache\system_processing_system7_0_wrapper.ngc (498210, 2012-10-09)
Lab4\implementation\fpga.flw (4040, 2012-10-09)
Lab4\implementation\netlist.lst (332, 2012-10-09)
Lab4\implementation\par_usage_statistics.html (4011, 2012-10-09)
Lab4\implementation\processing_system7_0_wrapper\processing_system7_0.xdc (27247, 2012-10-09)
Lab4\implementation\system.bgn (4374, 2012-10-09)
Lab4\implementation\system.bit (4045655, 2012-10-09)
Lab4\implementation\system.bld (10806, 2012-10-09)
Lab4\implementation\system.bmm (61, 2012-10-09)
Lab4\implementation\system.drc (184, 2012-10-09)
Lab4\implementation\system.ncd (210217, 2012-10-09)
... ...

TABLE OF CONTENTS 1) Peripheral Summary 2) Description of Generated Files 3) Location to documentation of dependent libraries ================================================================================ * 1) Peripheral Summary * ================================================================================ Peripheral Summary: XPS project / EDK repository : D:\_prj\Xilinx\Blog\Lab4 logical library name : my_axi_ip_v1_00_a top name : my_axi_ip version : 1.00.a type : AXI4LITE slave features : slave attachment user s/w registers Address Block for User Logic and IPIF Predefined Services user logic slave space : C_BASEADDR + 0x00000000 : C_BASEADDR + 0x000000FF ================================================================================ * 2) Description of Generated Files * ================================================================================ - HDL source file(s) hdl/vhdl/my_axi_ip.vhd This is the template file for your peripheral's top design entity. It configures and instantiates the corresponding design units in the way you indicated in the wizard GUI and hooks it up to the stub user logic where the actual functionalites should get implemented. You are not expected to modify this template file except certain marked places for adding user specific generics and ports. verilog/user_logic.v This is the template file for the stub user logic design entity, either in VHDL or Verilog, where the actual functionalities should get implemented. Some sample code snippet may be provided for demonstration purpose. - XPS interface file(s) data/my_axi_ip_v2_1_0.mpd This Microprocessor Peripheral Description file contains information of the interface of your peripheral, so that other EDK tools can recognize your peripheral. data/my_axi_ip_v2_1_0.pao This Peripheral Analysis Order file defines the analysis order of all the HDL source files that are used to compile your peripheral. - ISE project file(s) devl/projnav/my_axi_ip.xise This is the ProjNavigator project file. It sets up the needed logical libraries and dependent library files for you to help you develop your peripheral using ProjNavigator. devl/projnav/my_axi_ip.tcl This is the TCL command line file used to generate the .xise file. - XST synthesis file(s) devl/synthesis/my_axi_ip_xst.scr This is the XST synthesis script file to compile your peripheral. Note: you may want to modify the device part option for your target. devl/synthesis/my_axi_ip_xst.prj This is the XST synthesis project file used by the above script file to compile your peripheral. - Driver source file(s) src/my_axi_ip.h This is the software driver header template file, which contains address offset of software addressable registers in your peripheral, as well as some common masks and simple register access macros or function declaration. src/my_axi_ip.c This is the software driver source template file, to define all applicable driver functions. src/my_axi_ip_selftest.c This is the software driver self test example file, which contain self test example code to test various hardware features of your peripheral. src/Makefile This is the software driver makefile to compile drivers. - Driver interface file(s) -user needs to add these to repositories path in SDK (Xilinx Tools-->Repositories) data/my_axi_ip_v2_1_0.mdd This is the Microprocessor Driver Definition file. data/my_axi_ip_v2_1_0.tcl This is the Microprocessor Driver Command file. - Other misc file(s) devl/ipwiz.opt This is the option setting file for the wizard batch mode, which should generate the same result as the wizard GUI mode. devl/README.txt This README file for your peripheral. devl/ipwiz.log This is the log file by operating on this wizard. ================================================================================ * 3) Location to documentation of dependent libraries * * * * In general, the documentation is located under: * * $XILINX_EDK/hw/XilinxProcessorIPLib/pcores/$libName/doc * * * ================================================================================ proc_common_v3_00_a No documentation for this library axi_lite_ipif_v1_01_a D:\_prj\Xilinx\Blog\Lab4\C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_lite_ipif_v1_01_a\doc\axi_lite_ipif_ds765.pdf

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