and1
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：35KB
下载次数：10
上传日期：2007-01-19 22:13:33
上 传 者：
3215
说明： 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加
(using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum)
文件列表:
and1\and1(1).cnf (12196, 2006-12-19)
and1\and1(2).cnf (6939, 2006-12-19)
and1\and1(3).cnf (22584, 2006-12-19)
and1\and1(4).cnf (2881, 2006-12-19)
and1\and1(5).cnf (1851, 2006-12-19)
and1\and1.acf (15679, 2007-01-12)
and1\and1.cnf (45788, 2007-01-12)
and1\and1.fit (4414, 2007-01-12)
and1\and1.hif (4117, 2007-01-12)
and1\and1.mmf (238, 2007-01-12)
and1\and1.ndb (16786, 2007-01-12)
and1\and1.pin (3519, 2007-01-12)
and1\and1.pof (1963, 2007-01-12)
and1\and1.rpt (21702, 2007-01-12)
and1\and1.scf (2374, 2007-01-12)
and1\and1.snf (13348, 2007-01-12)
and1\AND1.sym (205, 2006-12-19)
and1\and1.vhd (763, 2007-01-12)
and1\LIB.DLS (106, 2007-01-12)
and1\U7992909.DLS (11618, 2007-01-12)
and1\U8548160.DLS (1328, 2007-01-12)
and1\U9829058.DLS (2728, 2007-01-12)
and1 (0, 2007-01-12)
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