文件列表:

WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\tests.v (21689, 2001-10-19)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\test_bench_top.v (23543, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\wb_mast_model.v (10767, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\wb_model_defines.v (3005, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\bench\verilog\wb_slv_model.v (5267, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\doc\conmax.pdf (105235, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\doc\STATUS.txt (660, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_arb.v (7807, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_defines.v (3151, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_master_if.v (20263, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_msel.v (7588, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_pri_dec.v (4276, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_pri_enc.v (5542, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_rf.v (9905, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_slave_if.v (12847, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\rtl\verilog\wb_conmax_top.v (118294, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\bin\Makefile (2363, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\ncwork\CVS\Entries (2, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\ncwork\CVS\Repository (33, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\ncwork\CVS\Root (13, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\waves\CVS\Entries (47, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\waves\CVS\Repository (32, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\waves\CVS\Root (13, 2007-03-31)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\sim\rtl_sim\run\waves\waves.do (10570, 2001-10-19)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\syn\bin\.read.dc.swp (12288, 2001-10-19)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\syn\bin\comp.dc (4610, 2002-10-03)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\syn\bin\design_spec.dc (706, 2001-10-19)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\syn\bin\lib_spec.dc (1123, 2001-10-19)
WISHBONE Interconnect Matrix IP CORE\wb_conmax\syn\bin\read.dc (1877, 2001-10-19)
8051\8051core-Verilog\8051core-Verilog\Acc.v (4294, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\All.v (12470, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\Alu.v (7500, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\alu_src1_sel.v (3667, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\alu_src2_sel.v (3503, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\alu_src3_sel.v (3312, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\Comp.v (3756, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\cy_select.v (3536, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\Decoder.v (84655, 2001-08-04)
8051\8051core-Verilog\8051core-Verilog\Defines.v (14435, 2001-08-04)
... ...

-- This code is provided for free and may be used and -- -- distributed without restriction provided that the -- -- copyright statement is not removed from the file and -- -- that any derivative work contains the original -- -- copyright notice and the associated disclaimer. -- -- Comments and suggestions are always welcome -- The i2c_master core consists of three files: - i2c_master_top -- top level - i2c_master_byte_ctrl -- byte controller - i2c_master_bit_ctrl -- bit controller VHDL needs to be compiled in order. The files are listed above in descending order. I2C.VHD and tst_ds1621.vhd are not supported anymore. They remain mostly for historical purposes, altough they might prove usefull. Richard Herveille rherveille@opencores.org

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