6_ImageBasic
所属分类：VHDL/FPGA/Verilog
开发工具：matlab
文件大小：14168KB
下载次数：84
上传日期：2014-01-19 20:38:40
上 传 者：
redhair
说明： 基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等
(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)
文件列表:
6_ImageBasic (0, 2012-10-22)
6_ImageBasic\6.1_Bypass (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SimulinkBypass (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SimulinkBypass\SimBypass.mdl (20426, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SysgenBypass\Bypass.mdl (37294, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\LoadImage.m (447, 2009-02-10)
6_ImageBasic\6.1_Bypass\SysgenBypass\ShowImage.m (561, 2009-02-10)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_ngo (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_ngo\netlist.lst (218, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs (0, 2012-10-22)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\bitgen.xmsgs (369, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\map.xmsgs (2136, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\ngdbuild.xmsgs (369, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\par.xmsgs (1018, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\trce.xmsgs (1041, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\_xmsgs\xst.xmsgs (5555, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass.vhd (67029, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.bgn (4611, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.bit (283852, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.bld (1207, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.cmd_log (1338, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.drc (131, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ise (264994, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.lso (6, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ncd (3634, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ngc (3228, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ngd (6576, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ngr (4638, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ntrc_log (122, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.pad (13581, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.par (2691, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.pcf (215, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.prj (51, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.ptwx (16463, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.restore (58723, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.sdc (47, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.sgp (0, 2009-03-26)
6_ImageBasic\6.1_Bypass\SysgenBypass\netlist\bypass_cw.stx (0, 2009-03-26)
... ...
The following files were generated for 'bmg_24_s3e_78f72cbe803be608' in directory
.\:
bmg_24_s3e_78f72cbe803be608.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
bmg_24_s3e_78f72cbe803be608.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
bmg_24_s3e_78f72cbe803be608.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
bmg_24_s3e_78f72cbe803be608.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
bmg_24_s3e_78f72cbe803be608.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
bmg_24_s3e_78f72cbe803be608.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
bmg_24_s3e_78f72cbe803be608.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
bmg_24_s3e_78f72cbe803be608_blk_mem_gen_v2_4_xst_1.ndf:
Optional output file produced for cores that generate NGC files.
The NDF files allow third party synthesis tools to infer resource
utilization and timing from the NGC files associated with these new
cores.
bmg_24_s3e_78f72cbe803be608_blk_mem_gen_v2_4_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
bmg_24_s3e_78f72cbe803be608_blk_mem_gen_v2_4_xst_1_vhdl.prj:
Please see the core data sheet.
bmg_24_s3e_78f72cbe803be608_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
bmg_24_s3e_78f72cbe803be608_readme.txt:
Text file indicating the files generated and how they are used.
bmg_24_s3e_78f72cbe803be608_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：