文件列表:

XAPP_585 (0, 2014-01-21)
XAPP_585\ucf (0, 2014-01-21)
XAPP_585\ucf\top5x2_7to1_ddr_rx.ucf (5702, 2013-10-15)
XAPP_585\ucf\top5x2_7to1_ddr_tx.ucf (4521, 2013-10-15)
XAPP_585\ucf\top5x2_7to1_sdr_rx.ucf (5204, 2013-10-15)
XAPP_585\ucf\top5x2_7to1_sdr_tx.ucf (4521, 2013-10-15)
XAPP_585\Verilog_macros (0, 2014-01-21)
XAPP_585\Verilog_macros\clock_generator_pll_7_to_1_diff_ddr.v (15176, 2013-10-15)
XAPP_585\Verilog_macros\clock_generator_pll_7_to_1_diff_sdr.v (14005, 2013-10-15)
XAPP_585\Verilog_macros\gearbox_4_to_7.v (7558, 2013-10-15)
XAPP_585\Verilog_macros\n_x_serdes_1_to_7_mmcm_idelay_ddr.v (7937, 2013-10-15)
XAPP_585\Verilog_macros\n_x_serdes_1_to_7_mmcm_idelay_sdr.v (7614, 2013-10-15)
XAPP_585\Verilog_macros\n_x_serdes_7_to_1_diff_ddr.v (4579, 2013-10-15)
XAPP_585\Verilog_macros\n_x_serdes_7_to_1_diff_sdr.v (4483, 2013-10-15)
XAPP_585\Verilog_macros\serdes_1_to_7_mmcm_idelay_ddr.v (34110, 2013-10-15)
XAPP_585\Verilog_macros\serdes_1_to_7_mmcm_idelay_sdr.v (29651, 2013-10-15)
XAPP_585\Verilog_macros\serdes_1_to_7_slave_idelay_ddr.v (22220, 2013-10-15)
XAPP_585\Verilog_macros\serdes_1_to_7_slave_idelay_sdr.v (19783, 2013-10-15)
XAPP_585\Verilog_macros\serdes_7_to_1_diff_ddr.v (14484, 2013-10-15)
XAPP_585\Verilog_macros\serdes_7_to_1_diff_sdr.v (7300, 2013-10-15)
XAPP_585\Verilog_testbench (0, 2014-01-21)
XAPP_585\Verilog_testbench\tb_top5x2_7to1_ddr.v (4333, 2013-10-15)
XAPP_585\Verilog_testbench\tb_top5x2_7to1_sdr.v (4333, 2013-10-15)
XAPP_585\Verilog_top_level_examples (0, 2014-01-21)
XAPP_585\Verilog_top_level_examples\top5x2_7to1_ddr_rx.v (5893, 2013-10-15)
XAPP_585\Verilog_top_level_examples\top5x2_7to1_ddr_tx.v (6059, 2013-10-15)
XAPP_585\Verilog_top_level_examples\top5x2_7to1_sdr_rx.v (5856, 2013-10-15)
XAPP_585\Verilog_top_level_examples\top5x2_7to1_sdr_tx.v (5962, 2013-10-15)
XAPP_585\VHDL_macros (0, 2014-01-21)
XAPP_585\VHDL_macros\clock_generator_pll_7_to_1_diff_ddr.vhd (14669, 2013-10-15)
XAPP_585\VHDL_macros\clock_generator_pll_7_to_1_diff_sdr.vhd (13329, 2013-10-15)
XAPP_585\VHDL_macros\gearbox_4_to_7.vhd (8672, 2013-10-15)
XAPP_585\VHDL_macros\n_x_serdes_1_to_7_mmcm_idelay_ddr.vhd (13067, 2013-10-15)
XAPP_585\VHDL_macros\n_x_serdes_1_to_7_mmcm_idelay_sdr.vhd (12426, 2013-10-15)
XAPP_585\VHDL_macros\n_x_serdes_7_to_1_diff_ddr.vhd (5875, 2013-10-15)
XAPP_585\VHDL_macros\n_x_serdes_7_to_1_diff_sdr.vhd (5671, 2013-10-15)
XAPP_585\VHDL_macros\serdes_1_to_7_mmcm_idelay_ddr.vhd (38281, 2013-10-15)
XAPP_585\VHDL_macros\serdes_1_to_7_mmcm_idelay_sdr.vhd (32399, 2013-10-15)
XAPP_585\VHDL_macros\serdes_1_to_7_slave_idelay_ddr.vhd (25745, 2013-10-15)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2012 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.0 Date Last Modified: June 27th 2012 Date Created: May 30th 2012 Associated Filename: xapp585.zip Associated Document: xapp585, LVDS Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication Supported Device(s): Virtex-7 FPGAs Kintex-7 FPGAs Artix-7 FPGAs ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. OTHER INFORMATION (OPTIONAL) 7. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= June 27th 2012 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with XAPP585 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Xilinx ISE 13.4 or higher (Includes XST, ISIM, and PlanAhead). 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder (XAPP585) is described below : \readme.txt - this file | \xapp585_Uncertainties_tool_1.0.xlsx - uncertainty calculator spreadsheet | \ucf | Contains example .ucf files for SDR and DDR based designs | \Verilog_macros | Contains the verilog macros for SDR and DDR based designs | \Verilog_testbench | Contains the verilog testbenches for SDR and DDR based designs | \Verilog_top_level_examples | Contains the verilog top level examples for SDR and DDR based designs | \VHDL_macros | Contains the VHDL macros for SDR and DDR based designs | \Verilog_testbench | Contains the VHDL testbenches for SDR and DDR based designs | \Verilog_top_level_examples Contains the VHDL top level examples for SDR and DDR based designs 5. INSTALLATION AND OPERATING INSTRUCTIONS Choose whether your design needs SDR or DDR techniques using the application note and enclosed spreadsheet. Install the Xilinx ISE 13.4 or later tools. To incorporate the appropriate module into an ISE design project: Verilog flow: 1) For SDR receiver designs, instantiate the receiver module n_x_serdes_1_to_7_mmcm_idelay_sdr.v and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 2) For SDR transmitter designs, instantiate the receiver module n_x_serdes_7_to_1_diff_sdr.v and the clock generator module clock_generator_pll_7_to_1_diff_sdr.v and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 3) For DDR receiver designs, instantiate the receiver module n_x_serdes_1_to_7_mmcm_idelay_ddr.v and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 4) For DDR transmitter designs, instantiate the receiver module n_x_serdes_7_to_1_diff_ddr.v and the clock generator module clock_generator_pll_7_to_1_diff_ddr.v and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 5) For designs containing both a receiver and a transmitter, the clock from the reciver module can be used for transmission instead of those from the clock generator module VHDL flow: 1) For SDR receiver designs, instantiate the receiver module n_x_serdes_1_to_7_mmcm_idelay_sdr.vhd and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 2) For SDR transmitter designs, instantiate the receiver module n_x_serdes_7_to_1_diff_sdr.vhd and the clock generator module clock_generator_pll_7_to_1_diff_sdr.vhd and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 3) For DDR receiver designs, instantiate the receiver module n_x_serdes_1_to_7_mmcm_idelay_ddr.vhd and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 4) For DDR transmitter designs, instantiate the receiver module n_x_serdes_7_to_1_diff_ddr.vhd and the clock generator module clock_generator_pll_7_to_1_diff_ddr.vhd and set the number of channels (N) and number of data-bits per channel (D) appropriately for the application. An example top-level design for 2 channels of 5-bits each is provided in the .zip file 5) For designs containing both a receiver and a transmitter, the clock from the reciver module can be used for transmission instead of those from the clock generator module 6. OTHER INFORMATION (OPTIONAL) 1) Warnings 2) Design Notes 3) Fixes 4) Known Issues When processing these designs with ISE version 14.1, map will possibly give an error. The fix for this condition is to set the "-ignore_keep_hierarchy" option in map, either via the graphical user interface, or as a command line option. 7. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.

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