文件列表:

i2c_master_slave_core\doc\i2c_core_verification_plan.pdf (305170, 2008-06-27)
i2c_master_slave_core\doc\i2c_spec.doc (571392, 2008-06-27)
i2c_master_slave_core\doc\i2c_spec.pdf (835279, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\config.sv (808, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\sb_callback.sv0000644 (2891, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_clkgen.sv (634, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_callback.sv (473, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_coverage.sv (6614, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_data_packet.sv (1228, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_driver.sv (27670, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_env.sv0000644 (4649, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_interface.sv (2210, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_monitor.sv (6448, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_mon_pkt.sv (1574, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_reg_pkt.sv (1428, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_sb_pkt.sv (1483, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_scenario_generator.sv (5971, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_scenario_packet.sv (2078, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_scoreboard.sv (6996, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_slave_driver.sv (20925, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_stimulus_packet.sv (2909, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_top.sv0000644 (1894, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_program1_test.sv (4092, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb\vmm_program_test.sv (764, 2008-06-27)
i2c_master_slave_core\verilog\rtl\controller_interface.v (10560, 2012-02-23)
i2c_master_slave_core\verilog\rtl\controller_interface.v.bak (12477, 2008-06-27)
i2c_master_slave_core\verilog\rtl\counter.v (1138, 2012-02-23)
i2c_master_slave_core\verilog\rtl\counter.v.bak (1252, 2008-06-27)
i2c_master_slave_core\verilog\rtl\i2c_blk.v (4821, 2012-02-23)
i2c_master_slave_core\verilog\rtl\i2c_blk.v.bak (5004, 2008-06-27)
i2c_master_slave_core\verilog\rtl\ms_core.v (25996, 2012-02-23)
i2c_master_slave_core\verilog\rtl\ms_core.v.bak (25957, 2012-02-23)
i2c_master_slave_core\verilog\rtl\shift.v (1429, 2012-02-23)
i2c_master_slave_core\verilog\rtl\shift.v.bak (1543, 2008-06-27)
i2c_master_slave_core\svtb\vmm_svtb (0, 2012-02-23)
i2c_master_slave_core\verilog\rtl (0, 2012-02-23)
i2c_master_slave_core\doc (0, 2012-02-23)
i2c_master_slave_core\svtb (0, 2012-02-23)
i2c_master_slave_core\verilog (0, 2012-02-23)
... ...

This Directory contains all files which are required to run this VMM testbench. Scripts are not given as it vary from compiler to compiler. The Basic structure of file system is given below. vmm_i2c_top.sv | |--- vmm_clkgen.sv |--- vmm_program_test.sv | |--- vmm_i2c_env.sv (This is the environment file and all transactors and packet files are included in this file) Please note that for transition coverage in register testcase (write-write-read), another file is availabe which is vmm_program1_test.sv. In this file Scenario_generator_class is extended and program and top level module is also available.

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