GTX_pcie_circle
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6230KB
下载次数：42
上传日期：2014-02-11 16:08:30
上 传 者：
Echo818
说明： ise v6开发板 外部pcei连接线 用GTX收发器实现自环回收发 可以用chipscpoe查看数据
(ise v6 development board outside pcei cable with GTX transceivers to achieve self-loop recycling hair can be used to view data chipscpoe)
文件列表:
test_10_12_1 (0, 2013-11-12)
test_10_12_1\10__17_selfdata.PNG (67616, 2013-10-17)
test_10_12_1\10——17两台电脑同时下.PNG (53394, 2013-10-17)
test_10_12_1\iseconfig (0, 2013-10-17)
test_10_12_1\iseconfig\v6_gtxwizard_v1_12.projectmgr (10300, 2013-11-12)
test_10_12_1\iseconfig\v6_gtxwizard_v1_12_top.xreport (21250, 2013-11-12)
test_10_12_1\test1.cdc (6250, 2013-10-17)
test_10_12_1\test1.cgc (135349, 2013-10-12)
test_10_12_1\test1.cgp (522, 2013-10-12)
test_10_12_1\tmp (0, 2013-10-17)
test_10_12_1\tmp\_cg (0, 2013-10-17)
test_10_12_1\tmp\_cg\_dbg (0, 2013-10-17)
test_10_12_1\tmp\_cg\_dbg\xil_582.in (1883, 2013-10-12)
test_10_12_1\tmp\_cg\_dbg\xil_582.out (116, 2013-10-12)
test_10_12_1\tmp\_xmsgs (0, 2013-10-17)
test_10_12_1\tmp\_xmsgs\pn_parser.xmsgs (573, 2013-10-12)
test_10_12_1\usage_statistics_webtalk.html (163281, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12 (0, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12.gise (15429, 2013-11-12)
test_10_12_1\v6_gtxwizard_v1_12.v (20525, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12.veo (12468, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12.xco (12314, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12.xise (39880, 2013-10-25)
test_10_12_1\v6_gtxwizard_v1_12\doc (0, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\doc\ug516_v6_gtxwizard.pdf (3376991, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\doc\v6_gtxwizard_v1_12_vinfo.html (5940, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\example_design (0, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\example_design\frame_check.v (26914, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\example_design\frame_gen.v (18357, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\example_design\gtx_attributes.ucf (43237, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\example_design\v6_gtxwizard_v1_12_rx_sync.v (8985, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\example_design\v6_gtxwizard_v1_12_top.sdc (2932, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\example_design\v6_gtxwizard_v1_12_top.ucf (4524, 2013-10-19)
test_10_12_1\v6_gtxwizard_v1_12\example_design\v6_gtxwizard_v1_12_top.v (68163, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\example_design\v6_gtxwizard_v1_12_top.xcf (2976, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\implement (0, 2013-10-17)
test_10_12_1\v6_gtxwizard_v1_12\implement\chipscope_project.cpj (144257, 2013-10-12)
test_10_12_1\v6_gtxwizard_v1_12\implement\data_vio.ngc (332059, 2012-07-21)
test_10_12_1\v6_gtxwizard_v1_12\implement\icon.ngc (53974, 2012-07-21)
test_10_12_1\v6_gtxwizard_v1_12\implement\ila.ngc (378182, 2012-07-21)
... ...
The following files were generated for 'icon_pro' in directory
E:\PROJECT\Debug\test_10_12\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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