CPLDLCD1602
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3461KB
下载次数：8
上传日期：2014-02-28 10:39:23
上 传 者：
gzhn8158
说明： CPLD控制液晶字符屏LCD1602显示
(CPLD CONTROL LCD1602)
文件列表:
CPLDLCD1602 (0, 2014-01-07)
CPLDLCD1602\an497.pdf (136020, 2009-11-07)
CPLDLCD1602\an497_CN.pdf (303034, 2009-12-10)
CPLDLCD1602\an497_design_example.zip (1584924, 2009-11-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler (0, 2007-11-09)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\code (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\code\lcd_controller.v (24435, 2007-11-24)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\lcd_controller.cr.mti (1449, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\lcd_controller.mpf (10006, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\lcd_controller.v (24435, 2007-11-24)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\lcd_testbench.v (2739, 2007-01-25)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\transcript (490, 2007-02-08)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\vsim.wlf (1335296, 2007-02-08)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\wave.bmp (209374, 2007-02-08)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\wave.do (1091, 2007-02-08)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2 (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2\verilog.psm (5073, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2\_primary.dat (641, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2\_primary.vhd (380, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2_altufm_parallel_bmm (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2_altufm_parallel_bmm\verilog.psm (89217, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2_altufm_parallel_bmm\_primary.dat (8749, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\@u@f@m2_altufm_parallel_bmm\_primary.vhd (420, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\divider (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\divider\verilog.psm (3130, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\divider\_primary.dat (323, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\divider\_primary.vhd (176, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\fsm (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\fsm\verilog.psm (32583, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\fsm\_primary.dat (3743, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\fsm\_primary.vhd (1099, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_controller (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_controller\verilog.psm (4761, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_controller\_primary.dat (636, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_controller\_primary.vhd (529, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_testbench (0, 2014-01-07)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_testbench\verilog.psm (11986, 2007-11-27)
CPLDLCD1602\LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\modelsim\work\lcd_testbench\_primary.dat (1519, 2007-11-27)
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