dpd_v6_0_example_design
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1951KB
下载次数：61
上传日期：2014-03-01 10:26:47
上 传 者：
laole
说明： xilink DPD V6.0 IP Core design example
文件列表:
dpd_v6_0_example_design\dfe_base.prj (5110, 2012-10-17)
dpd_v6_0_example_design\dfe_base.vhd (53810, 2012-10-25)
dpd_v6_0_example_design\dpd_v6_0_demo_msdpdgen1p5.cgp (515, 2012-10-15)
dpd_v6_0_example_design\dpd_v6_0_demo_msdpdgen1p5.ucf (46485, 2012-10-16)
dpd_v6_0_example_design\dpd_v6_0_demo_msdpdgen1p5.xst (1048, 2012-10-15)
dpd_v6_0_example_design\dpd_v6_0_inst.xco (1465, 2012-10-15)
dpd_v6_0_example_design\iter6_pc_cfr_v3_0.xco (1944, 2012-10-24)
dpd_v6_0_example_design\Makefile (4143, 2012-10-15)
dpd_v6_0_example_design\src (0, 2012-10-31)
dpd_v6_0_example_design\src\clk_gen (0, 2012-10-31)
dpd_v6_0_example_design\src\clk_gen\hdl (0, 2012-10-31)
dpd_v6_0_example_design\src\clk_gen\hdl\clk_gen_src368mhz.vhd (8728, 2012-10-15)
dpd_v6_0_example_design\src\clk_gen\hdl\data_path_clk_gen_src200mhz.vhd (8857, 2012-10-15)
dpd_v6_0_example_design\src\clk_gen\hdl\proc_clk_gen_src200mhz.vhd (8603, 2012-10-15)
dpd_v6_0_example_design\src\device (0, 2012-10-31)
dpd_v6_0_example_design\src\device\common (0, 2012-10-31)
dpd_v6_0_example_design\src\device\common\hdl (0, 2012-10-31)
dpd_v6_0_example_design\src\device\common\hdl\dfe_capture_control.vhd (9075, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_complex_fir.vhd (7377, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_complex_fir_x0_h0h1.vhd (5657, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_complex_fir_x0x1_h0.vhd (5647, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_config_registers.vhd (3675, 2012-10-17)
dpd_v6_0_example_design\src\device\common\hdl\dfe_dlb.vhd (9276, 2012-07-03)
dpd_v6_0_example_design\src\device\common\hdl\dfe_dlb_wrapper.vhd (7593, 2012-07-03)
dpd_v6_0_example_design\src\device\common\hdl\dfe_dpram_piped_rtl.vhd (10039, 2012-10-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_fh_gen_adder_12x16bit.vhd (7121, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_fh_gen_adder_3x48bit.vhd (13344, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_gain_iq_mult.vhd (4707, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_generic_equalizer.vhd (6127, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_glitch_protection.vhd (8472, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_pipeliner.vhd (3694, 2012-08-10)
dpd_v6_0_example_design\src\device\common\hdl\dfe_polyphase_complex_fir.vhd (12434, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_rate_change.vhd (6933, 2012-06-08)
dpd_v6_0_example_design\src\device\common\hdl\dfe_systolic_fir.vhd (5253, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_systolic_fir_preadd_coeffs.vhd (6719, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_systolic_fir_preadd_data.vhd (6547, 2012-06-04)
dpd_v6_0_example_design\src\device\common\hdl\dfe_up2.vhd (6126, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_up3_dn2.vhd (14356, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_up3_dn2_polyphase.vhd (16708, 2012-10-15)
dpd_v6_0_example_design\src\device\common\hdl\dfe_up3_dn2_polyphase_2x2.vhd (9282, 2012-10-15)
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