Project
所属分类：加密解密
开发工具：VHDL
文件大小：58KB
下载次数：6
上传日期：2014-03-05 05:45:23
上 传 者：
yyang39
说明： 基于FPGA的AES算法的VHDL实现，低内存模式
(aes vhdl code)
文件列表:
iseconfig\aes_top_module.xreport (20814, 2013-12-18)
iseconfig\Project.projectmgr (7329, 2013-12-18)
xst\work\hdllib.ref (773, 2013-12-18)
xst\work\hdpdeps.ref (1802, 2013-12-18)
xst\work\sub00\vhpl00.vho (2673, 2013-12-18)
xst\work\sub00\vhpl01.vho (781, 2013-12-18)
xst\work\sub00\vhpl02.vho (1072, 2013-12-18)
xst\work\sub00\vhpl03.vho (3861, 2013-12-18)
xst\work\sub00\vhpl04.vho (66351, 2013-12-18)
xst\work\sub00\vhpl05.vho (892, 2013-12-18)
xst\work\sub00\vhpl06.vho (4864, 2013-12-18)
xst\work\sub00\vhpl07.vho (777, 2013-12-18)
xst\work\sub00\vhpl08.vho (1503, 2013-12-18)
xst\work\sub00\vhpl09.vho (1034, 2013-12-18)
.lso (6, 2013-12-18)
aes_data_types.vhd (783, 2013-12-18)
aes_top_module.cmd_log (188, 2013-12-18)
aes_top_module.lso (6, 2013-12-18)
aes_top_module.prj (211, 2013-12-18)
aes_top_module.stx (2677, 2013-12-18)
aes_top_module.syr (4397, 2013-12-18)
aes_top_module.vhd (3249, 2013-12-18)
aes_top_module.xst (124, 2013-12-18)
aes_top_module_envsettings.html (9666, 2013-12-18)
aes_top_module_summary.html (4139, 2013-12-18)
aes_top_module_vhdl.prj (266, 2013-12-18)
aes_top_module_xst.xrpt (8882, 2013-12-18)
fctns.vhd (11162, 2013-12-18)
mix_col.vhd (2244, 2013-12-18)
Project.gise (5610, 2013-12-18)
Project.xise (35752, 2013-12-18)
qwe.vhd (1726, 2013-12-18)
sbox_calc.prj (92, 2013-12-18)
sbox_calc.stx (1279, 2013-12-18)
sbox_calc.vhd (2008, 2013-12-18)
sbox_calc.xst (119, 2013-12-18)
sbox_calc_summary.html (3664, 2013-12-18)
sbox_calc_vhdl.prj (103, 2013-12-18)
shift_rows.prj (60, 2013-12-18)
shift_rows.stx (1210, 2013-12-18)
... ...
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