SystemVerilog

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:7503KB
下载次数:21
上传日期:2014-03-05 21:17:34
上 传 者3271854
说明:  本书重点介绍硬件设计描述和验证语言SystemVerilog的基本语法及其在功能验证上的应 用;书中以功能验证为主线,讲述基本的验证流程、高级验证技术和验证方法学,以Sys temVerilog为基础结合石头、剪刀、布的应用实例,重点阐述了如何采用SystemVerilog实现 随机激励生成、功能覆盖率驱动验证、断言验证等多种高级验证技术;最后,通过业界流行 的开放式验证方法学OVM介绍如何在验证平台中实现可重用性。
(The basic syntax and its application describes the book focuses on the hardware design and verification language SystemVerilog in the functional verification book to functional verification, tells the basic verification process, advanced verification technology and verification methodology to Sys  temVerilog as the basis of combining rock, scissors, cloth application examples, focusing on how to achieve using SystemVerilog random stimulus generation, functional coverage-driven verification, validation, and other senior assertion verification technologies Finally, the industry' s popular OVM Open Verification Methodology Introduction How to achieve reusability in verification platform.)

文件列表:
SystemVerilog与功能验证.pdf (9370332, 2013-10-24)

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