vhtoverilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：28634KB
下载次数：3
上传日期：2014-03-07 20:08:22
上 传 者：
shankar
说明： A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test
response compaction are the unknown values (x-values) captured
by scan cells during testing. If test responses with
x-values are compacted, some of the outputs of the compactor
may also take unknown values and the correctness of the
compactor inputs cannot be verified at the compactor outputs.
The presence of x-values hence reduces observability of (nonx)
scan cells that may lead to a reduction of test quality and/or
limited compaction rates
文件列表:
vhtoverilog\14SEP2013\bin\verilog2vhdl (1012, 2013-02-12)
vhtoverilog\14SEP2013\bin\verilog2vhdl.bat (863, 2013-02-08)
vhtoverilog\14SEP2013\bin\verilog2vhdlcomponent (1028, 2013-02-12)
vhtoverilog\14SEP2013\bin\verilog2vhdlcomponent.bat (863, 2013-02-08)
vhtoverilog\14SEP2013\bin\verilog2vhdlentity (1023, 2013-02-12)
vhtoverilog\14SEP2013\bin\verilog2vhdlentity.bat (876, 2013-02-08)
vhtoverilog\14SEP2013\examples\simple_and\output.v2vh.vhd (5851, 2013-05-18)
vhtoverilog\14SEP2013\examples\simple_and\runme.bat (69, 2012-12-01)
vhtoverilog\14SEP2013\examples\simple_and\runme.csh (84, 2012-11-29)
vhtoverilog\14SEP2013\examples\simple_and\simple_and.v (804, 2012-02-04)
vhtoverilog\14SEP2013\examples\simple_and\simple_and.vhd (5851, 2013-05-18)
vhtoverilog\14SEP2013\examples\simple_and\verilog2vhdl.log (4398, 2013-05-18)
vhtoverilog\14SEP2013\lib\designplayer.jar (31491354, 2013-09-14)
vhtoverilog\14SEP2013\LICENSE.txt (1424, 2013-02-09)
vhtoverilog\14SEP2013\log (850199, 2013-05-20)
vhtoverilog\14SEP2013\setup_env.bat (183, 2013-02-13)
vhtoverilog\14SEP2013\setup_env.csh (800, 2013-02-12)
vhtoverilog\14SEP2013\setup_env.sh (825, 2013-02-12)
vhtoverilog\14SEP2013\sum (7585, 2013-05-20)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\math_complex\body.dmp (219395, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\math_complex\math_complex.dmp (49871, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\math_real\body.dmp (137863, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\math_real\math_real.dmp (29820, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\numeric_bit\body.dmp (345296, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\numeric_bit\numeric_bit.dmp (63299, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\numeric_std\body.dmp (515667, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\numeric_std\numeric_std.dmp (98095, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_1164\body.dmp (172202, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_1164\std_logic_1164.dmp (37673, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_arith\body.dmp (407247, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_arith\std_logic_arith.dmp (105522, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_arith_ext\body.dmp (267941, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_arith_ext\std_logic_arith_ext.dmp (85460, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_misc\body.dmp (212059, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_misc\std_logic_misc.dmp (66103, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_signed\body.dmp (201518, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_signed\std_logic_signed.dmp (164118, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_textio\body.dmp (194265, 2013-04-06)
vhtoverilog\14SEP2013\vhdl_pkgs\lib\ieee\std_logic_textio\std_logic_textio.dmp (90457, 2013-04-06)
... ...
**************************************************************************
* *
* Verilog To VHDL Converter *
* Copyright (C) 2012, edautils.com *
* *
**************************************************************************
Welcome to this free Verilog To VHDL Converter!
This utility is meant for those users who wants to convert
their Verilog design into VHDL . This utility has been implemented in
Java and packaged as a JAR file. Goto installation area and source
the setup_env file to setup the environment for this tool.
You need to execute this utility as -
verilog2vhdl -in simple_and.v -top simple_and -out output.vhd
OR
java com.eu.miscedautils.verilog2vhdl.verilog2vhdl -in simple_and.v -top simple_and -out output.vhd
There are options like -only_entity to create just only the entity.
Also, there are options like -only_component a component
declaration corresponding to the specified top module.
FYI- you need Java 1.6.x or above to run this utility.
See the example(s) to understand the usage better.
For any assistance contact help@edautils.com .
FEEDBACK
========
Send feedback to help@edautils.com
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