Verilog_Development_Board_Sources
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：3078KB
下载次数：363
上传日期：2007-02-09 10:41:31
上 传 者：
jawen
说明： 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟
(friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock)
文件列表:
248814\Verilog\基础实验\加法器\db\add.cbx.xml (85, 2005-10-12)
248814\Verilog\基础实验\二进制转BCD码\db\bcd.cbx.xml (181, 2005-12-14)
248814\Verilog\接口实验\蜂鸣器\db\buzzer.cbx.xml (187, 2005-12-14)
248814\Verilog\综合实验\数字时钟\db\clock.cbx.xml (185, 2005-12-14)
248814\Verilog\基础实验\四位比较器\db\cmp.cbx.xml (85, 2005-10-12)
248814\Verilog\接口实验\拨码开关\db\dial.cbx.xml (86, 2005-12-14)
248814\Verilog\基础实验\除法器\db\div.cbx.xml (85, 2005-10-12)
248814\Verilog\基础实验\8位优先编码器\db\encode.cbx.xml (88, 2005-10-12)
248814\Verilog\接口实验\i2c总线\db\i2c.cbx.xml (277, 2005-12-14)
248814\Verilog\接口实验\矩阵键盘\key1\db\key1.cbx.xml (86, 2005-12-14)
248814\Verilog\接口实验\跑马灯\db\ledwater.cbx.xml (90, 2005-12-14)
248814\Verilog\基础实验\乘法器\db\mlt.cbx.xml (85, 2005-10-12)
248814\Verilog\基础实验\多路选择器\db\mux.cbx.xml (85, 2005-10-12)
248814\Verilog\接口实验\7段数码管\seg71\db\seg71.cbx.xml (87, 2005-12-14)
248814\Verilog\接口实验\串口\db\serial.cbx.xml (187, 2005-10-12)
248814\Verilog\基础实验\简单状态机\db\state_machine.cbx.xml (95, 2005-12-14)
248814\Verilog\基础实验\减法器\db\sub.cbx.xml (181, 2005-10-12)
248814\Verilog\综合实验\交通灯\db\traffic.cbx.xml (189, 2005-12-14)
248814\Verilog\接口实验\蜂鸣器\db\buzzer.smp_dump.txt (211, 2005-12-14)
248814\Verilog\接口实验\i2c总线\db\i2c.smp_dump.txt (760, 2005-12-14)
248814\Verilog\接口实验\矩阵键盘\key1\db\key1.smp_dump.txt (473, 2005-12-14)
248814\Verilog\接口实验\i2c总线\serv_req_info.txt (559, 2005-09-08)
248814\Verilog\基础实验\简单状态机\db\state_machine.smp_dump.txt (242, 2005-12-14)
248814\Verilog\综合实验\交通灯\db\traffic.smp_dump.txt (112, 2005-12-14)
248814\Verilog\基础实验\8位优先编码器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\乘法器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\除法器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\多路选择器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\加法器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\减法器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\四位比较器\cmp_state.ini (2, 2005-10-12)
248814\Verilog\基础实验\二进制转BCD码\cmp_state.ini (3, 2005-12-14)
248814\Verilog\基础实验\简单状态机\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\7段数码管\seg71\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\i2c总线\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\拨码开关\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\蜂鸣器\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\串口\cmp_state.ini (2, 2005-12-14)
248814\Verilog\接口实验\矩阵键盘\key1\cmp_state.ini (3, 2005-12-14)
248814\Verilog\接口实验\跑马灯\cmp_state.ini (3, 2005-12-14)
... ...
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