文件列表:

249006 (0, 2011-02-18)
249006\color_space_pkg.vhd (1311, 2006-01-19)
249006\GenXlib_arch.vhd (26339, 2006-04-18)
249006\GenXlib_utils.vhd (7521, 2006-04-10)
249006\sysgen (0, 2011-02-18)
249006\sysgen\double_rgb2ycrcb.m (1069, 2006-01-16)
249006\sysgen\double_ycrcb2rgb.m (1265, 2006-01-16)
249006\sysgen\wave_add_ycrcb.do (3410, 2006-03-14)
249006\sysgen\wave_add_ycrcb_v4.do (4484, 2006-04-18)
249006\sysgen\Xil_YCrCb2RGB_action.m (8681, 2006-03-14)
249006\sysgen\Xil_YCrCb2RGB_config.m (7460, 2006-04-18)
249006\sysgen\Xil_YCrCb2RGB_enablement.m (1330, 2006-03-13)
249006\sysgen\Xil_YCrCb2RGB_fi_model.m (4303, 2006-03-10)
249006\sysgen\Xil_YCrCb2RGB_GUI.xml (5484, 2006-03-14)
249006\sysgen\Xil_YCrCb2RGB_post_proc.m (1708, 2006-04-19)
249006\sysgen\Xil_YCrCb2RGB_preload_mdl.m (1650, 2006-04-19)
249006\sysgen\Xil_YCrCb2RGB_sg_wrap.vhd (8465, 2006-03-13)
249006\sysgen\Xil_YCrCb2RGB_tb.mdl (77509, 2006-04-18)
249006\Xil_YCrCb2RGB.vhd (22114, 2006-04-18)

******************************************************************************* ** Copyright 2006, Xilinx, Inc. ** This design is confidential and proprietary of Xilinx, Inc. All Rights Reserved. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: readme.txt ** / / Date Last Modified: Apr 13, 2006 ** /___/ /\ Date Created: Apr 13, 2006 ** \ \ / \ ** \___\/\___\ ** **Device: Spartan-3, Virtex-II, Virtex-II Pro, Virtex **Purpose: Color-space conversion, YCrCb to RGB domain **Reference: Recommendation ITU-R BT.601-5 standard definition; http://www.itu.int ** ******************************************************************************* ** ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is." Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, noninfringement, or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrant or ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits, cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply notwithstanding the failure of the ** essential purpose of any limited remedies herein. ** ******************************************************************************* This readme describes how to use the files that come with XAPP931. ******************************************************************************* ** IMPORTANT NOTES ** 1) To ensure proper conversion, generic parameters setting coefficient values may need to be modified. Please consult application note XAPP931 for parameter value assignment. 2) System Generator users: When changing the 'Input Bits' setting of the YCrCb2RGB token make sure the width of input channels R,G,B are adjusted accordingly. Also, verify coefficient and limit settings in the "Advanced" tab. ******************************************************************************* To incorporate the insert name here module into an ISE design project: VHDL flow: 1) Unzip the reference design files into a temporary directory. 2) Add all .vhd file from the root directory to your ISE project. 3) instantiate component YCrCb2RGB, and connect it to the proper signals in your design. A component declaration and instantiation template/example is provided in Xil_YCrCb2RGB_sg_wrap.vhd in the sysgen directory. System Generator flow: 1) Open the reference model Xil_YCrCb2RGB_tb.mdl in MATLAB. 2) Copy and paste the "ColorSpace Conversion YCrCb to RGB" token to your design. 3) If necessary, modify token parameters by double clicking the token. 4) Connect input and output signals while making sure signals are compatible with the token settings.

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