文件列表:

FPGA\DE1_SoC_ADC\.qsys_edit\filters.xml (68, 2013-09-03)
FPGA\DE1_SoC_ADC\.qsys_edit\preferences.xml (583, 2013-09-03)
FPGA\DE1_SoC_ADC\c5_pin_model_dump.txt (4875, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.cdf (433, 2013-10-16)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.done (26, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.fit.smsg (482, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.fit.summary (664, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.jdi (18959, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.map.smsg (3075, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.map.summary (533, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.pin (104759, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.qpf (110, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.qsf (45630, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.qws (882, 2013-11-07)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.sdc (2503, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.sof (6768487, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.sta.summary (9381, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_ADC.v (7748, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\DE1_SoC_QSYS.qip (24540, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\DE1_SoC_QSYS.v (51145, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_avalon_dc_fifo.v (26090, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_avalon_mm_clock_crossing_bridge.v (11533, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_avalon_sc_fifo.v (34467, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_avalon_st_pipeline_base.v (4705, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_avalon_st_pipeline_stage.sv (5451, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_dcfifo_synchronizer_bundle.v (883, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_irq_clock_crosser.sv (1640, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_arbitrator.sv (9530, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_burst_uncompressor.sv (13480, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_master_agent.sv (12421, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_master_translator.sv (21304, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_slave_agent.sv (28311, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_slave_translator.sv (17186, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_merlin_traffic_limiter.sv (38700, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_reset_controller.sdc (1734, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_reset_controller.v (12327, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\altera_reset_synchronizer.v (3553, 2013-11-06)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\DE1_SoC_QSYS_addr_router.sv (7965, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\DE1_SoC_QSYS_addr_router_001.sv (8487, 2013-09-03)
FPGA\DE1_SoC_ADC\DE1_SoC_QSYS\synthesis\submodules\DE1_SoC_QSYS_addr_router_002.sv (8401, 2013-09-03)
... ...

This template is starting point for creating a project based on your custom C code. It will provide you a default project to which you can add your software files. To add files to a project, manually copy the file into the application directory (e.g. using Windows Explorer), then right click on your application project and select refresh. You can also add files to the project using the Nios II Software Build Tools for Eclipse import function. Select File -> Import. Expand General and select File System in the Import Window and click Next. Identify the appropriate source and destination directories. Check the files you want to add and click Finish.

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