DSB
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1306KB
下载次数：48
上传日期：2014-04-09 15:40:54
上 传 者：
w783820717
说明： FPGA中实现的DSB的AM调制，带Modelsim仿真，实际测试通过：载波频率，信号频率以及调制度可调。
(The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.)
文件列表:
DSB (0, 2014-04-09)
DSB\Code (0, 2014-04-09)
DSB\Code\AM.v (895, 2014-03-04)
DSB\Code\AM_tb.v (362, 2014-04-09)
DSB\Code\AM_tb.v.bak (362, 2014-04-09)
DSB\Code\CarrierWave.v (1377, 2014-03-04)
DSB\Code\ModulateWave.v (1456, 2014-04-09)
DSB\Code\ModulateWave.v.bak (1456, 2014-03-04)
DSB\Code\Mult_10bs.v (4661, 2014-03-04)
DSB\Code\Mult_14BS.v (4665, 2014-03-04)
DSB\Code\sin.mif (10058, 2014-03-03)
DSB\Code\sin_rom_10b.v (6397, 2014-03-04)
DSB\Modelsim (0, 2014-04-09)
DSB\Modelsim\DSB.mpf (58850, 2014-04-09)
DSB\Modelsim\sin.mif (10058, 2014-03-03)
DSB\Modelsim\sin.ver (10992, 2014-04-09)
DSB\Modelsim\vsim.wlf (1327104, 2014-04-09)
DSB\Modelsim\work (0, 2014-04-09)
DSB\Modelsim\work\@a@m (0, 2014-04-09)
DSB\Modelsim\work\@a@m\verilog.asm (5096, 2014-04-09)
DSB\Modelsim\work\@a@m\verilog.rw (2138, 2014-04-09)
DSB\Modelsim\work\@a@m\_primary.dat (638, 2014-04-09)
DSB\Modelsim\work\@a@m\_primary.dbs (824, 2014-04-09)
DSB\Modelsim\work\@a@m\_primary.vhd (375, 2014-04-09)
DSB\Modelsim\work\@carrier@wave (0, 2014-04-09)
DSB\Modelsim\work\@carrier@wave\verilog.asm (7888, 2014-04-09)
DSB\Modelsim\work\@carrier@wave\verilog.rw (3220, 2014-04-09)
DSB\Modelsim\work\@carrier@wave\_primary.dat (828, 2014-04-09)
DSB\Modelsim\work\@carrier@wave\_primary.dbs (1531, 2014-04-09)
DSB\Modelsim\work\@carrier@wave\_primary.vhd (330, 2014-04-09)
DSB\Modelsim\work\@modulate@wave (0, 2014-04-09)
DSB\Modelsim\work\@modulate@wave\verilog.asm (7608, 2014-04-09)
DSB\Modelsim\work\@modulate@wave\verilog.rw (3115, 2014-04-09)
DSB\Modelsim\work\@modulate@wave\_primary.dat (808, 2014-04-09)
DSB\Modelsim\work\@modulate@wave\_primary.dbs (1552, 2014-04-09)
DSB\Modelsim\work\@modulate@wave\_primary.vhd (331, 2014-04-09)
DSB\Modelsim\work\@mult_10bs (0, 2014-04-09)
DSB\Modelsim\work\@mult_10bs\verilog.asm (6840, 2014-04-09)
DSB\Modelsim\work\@mult_10bs\verilog.rw (3102, 2014-04-09)
DSB\Modelsim\work\@mult_10bs\_primary.dat (815, 2014-04-09)
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