ata.tar
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：816KB
下载次数：1
上传日期：2014-04-24 17:46:35
上 传 者：
richman
说明： ATA Inteface Verilog Design
文件列表:
ata (0, 2008-05-15)
ata\syn (0, 2008-05-15)
ata\syn\log (0, 2008-05-15)
ata\syn\log\CVS (0, 2008-05-15)
ata\syn\log\CVS\Repository (12, 2008-05-15)
ata\syn\log\CVS\Entries (2, 2008-05-15)
ata\syn\log\CVS\Root (13, 2008-05-15)
ata\syn\out (0, 2008-05-15)
ata\syn\out\CVS (0, 2008-05-15)
ata\syn\out\CVS\Repository (12, 2008-05-15)
ata\syn\out\CVS\Entries (2, 2008-05-15)
ata\syn\out\CVS\Root (13, 2008-05-15)
ata\syn\bin (0, 2008-05-15)
ata\syn\bin\lib_spec.dc (1123, 2001-08-16)
ata\syn\bin\design_spec.dc (659, 2001-08-16)
ata\syn\bin\comp.dc (3875, 2001-08-16)
ata\syn\bin\read.dc (1877, 2001-08-16)
ata\syn\bin\CVS (0, 2008-05-15)
ata\syn\bin\CVS\Repository (12, 2008-05-15)
ata\syn\bin\CVS\Entries (173, 2008-05-15)
ata\syn\bin\CVS\Root (13, 2008-05-15)
ata\syn\CVS (0, 2008-05-15)
ata\syn\CVS\Repository (8, 2008-05-15)
ata\syn\CVS\Entries (40, 2008-05-15)
ata\syn\CVS\Root (13, 2008-05-15)
ata\syn\run (0, 2008-05-15)
ata\syn\run\CVS (0, 2008-05-15)
ata\syn\run\CVS\Repository (12, 2008-05-15)
ata\syn\run\CVS\Entries (2, 2008-05-15)
ata\syn\run\CVS\Root (13, 2008-05-15)
ata\documentation (0, 2008-05-15)
ata\documentation\CVS (0, 2008-05-15)
ata\documentation\CVS\Repository (18, 2008-05-15)
ata\documentation\CVS\Entries (2, 2008-05-15)
ata\documentation\CVS\Root (13, 2008-05-15)
ata\sim (0, 2008-05-15)
ata\sim\gate_sim (0, 2008-05-15)
ata\sim\gate_sim\bin (0, 2008-05-15)
ata\sim\gate_sim\bin\CVS (0, 2008-05-15)
ata\sim\gate_sim\bin\CVS\Repository (21, 2008-05-15)
... ...
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