light
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：20043KB
下载次数：35
上传日期：2014-04-25 12:31:51
上 传 者：
skylizer
说明： 基于FPGA的点灯游戏，完整工程。包括鼠标控制，键盘控制，SVGA显示等
(Light game based on FPGA, the whole project which includes keyboard control, SVGA and so on.)
文件列表:
lab19\ISE\light\.lso (6, 2012-06-26)
lab19\ISE\light\bit_counter.v (595, 2012-06-27)
lab19\ISE\light\buttom_mid_layer.v (7683, 2012-06-28)
lab19\ISE\light\ChangePos.v (1565, 2012-06-27)
lab19\ISE\light\Control.v (2596, 2012-06-27)
lab19\ISE\light\Control_ChangePos.v (603, 2012-06-25)
lab19\ISE\light\data_process.v (6703, 2012-06-25)
lab19\ISE\light\Display.v (1205, 2012-06-26)
lab19\ISE\light\div_3000.v (499, 2012-06-24)
lab19\ISE\light\d_ff.v (330, 2012-06-24)
lab19\ISE\light\indication.v (1681, 2012-06-27)
lab19\ISE\light\interface.v (1315, 2012-06-27)
lab19\ISE\light\light.ipf (3637, 2012-06-28)
lab19\ISE\light\light.ipf_ISE_Backup (3601, 2012-06-28)
lab19\ISE\light\light.ise (322969, 2012-06-28)
lab19\ISE\light\light.ise_ISE_Backup (322969, 2012-06-28)
lab19\ISE\light\light.ntrc_log (6784, 2012-06-28)
lab19\ISE\light\light.restore (51823, 2012-06-28)
lab19\ISE\light\ps2_controler.v (2849, 2012-06-27)
lab19\ISE\light\ps2_keyboard_top.v (1209, 2012-06-25)
lab19\ISE\light\select.v (700, 2012-06-28)
lab19\ISE\light\shift_reg.v (337, 2012-06-24)
lab19\ISE\light\SVGA.v (3336, 2012-06-24)
lab19\ISE\light\templates\coregen.xml (1292, 2012-06-26)
lab19\ISE\light\top_layer.v (13188, 2012-06-28)
lab19\ISE\light\top_together.bgn (7627, 2012-06-28)
lab19\ISE\light\top_together.bit (1448818, 2012-06-28)
lab19\ISE\light\top_together.bld (1554, 2012-06-28)
lab19\ISE\light\top_together.cel (0, 2012-06-27)
lab19\ISE\light\top_together.cmd_log (41747, 2012-06-28)
lab19\ISE\light\top_together.drc (542, 2012-06-28)
lab19\ISE\light\top_together.lfp (0, 2012-06-27)
lab19\ISE\light\top_together.lso (6, 2012-06-26)
lab19\ISE\light\top_together.ncd (235854, 2012-06-28)
lab19\ISE\light\top_together.ngc (248320, 2012-06-28)
lab19\ISE\light\top_together.ngd (371415, 2012-06-28)
lab19\ISE\light\top_together.ngr (715368, 2012-06-28)
lab19\ISE\light\top_together.pad (35732, 2012-06-28)
lab19\ISE\light\top_together.par (7307, 2012-06-28)
lab19\ISE\light\top_together.pcf (10542, 2012-06-28)
... ...
The following files were generated for 'zkROM' in directory
E:\lab19\ISE\light:
zkROM.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
zkROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
zkROM.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
zkROM.sym:
Please see the core data sheet.
zkROM.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
zkROM.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
zkROM.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
zkROM.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
zkROM.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
zkROM_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
zkROM_readme.txt:
Text file indicating the files generated and how they are used.
zkROM_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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