DPD_project
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8355KB
下载次数：56
上传日期：2014-04-26 15:45:21
上 传 者：
tioit
说明： 预失真算法中，包络解波部分的verilog代码，有部分错误
(envelope calculation of DPD algorithm ，verilong HDL language)
文件列表:
DPD_project\baud.cmd_log (210, 2014-03-30)
DPD_project\baud.tfi (149, 2014-03-30)
DPD_project\baud.v (2031, 2014-03-31)
DPD_project\carri_rom.cmd_log (225, 2014-03-13)
DPD_project\carri_rom.tfi (178, 2014-03-13)
DPD_project\carri_rom.v (2149, 2014-03-20)
DPD_project\DPD_abs.cmd_log (219, 2014-03-20)
DPD_project\DPD_abs.lso (6, 2014-03-21)
DPD_project\DPD_abs.prj (26, 2014-03-21)
DPD_project\DPD_abs.stx (1676, 2014-03-21)
DPD_project\DPD_abs.tfi (249, 2014-03-20)
DPD_project\DPD_abs.v (18420, 2014-03-20)
DPD_project\DPD_abs.xst (1140, 2014-03-21)
DPD_project\DPD_carri_maker_top.cmd_log (138, 2014-03-13)
DPD_project\DPD_carri_maker_top.lso (6, 2014-03-13)
DPD_project\DPD_carri_maker_top.ngc (2645, 2014-03-13)
DPD_project\DPD_carri_maker_top.ngr (2094, 2014-03-13)
DPD_project\DPD_carri_maker_top.prj (106, 2014-03-13)
DPD_project\DPD_carri_maker_top.stx (0, 2014-03-13)
DPD_project\DPD_carri_maker_top.syr (14398, 2014-03-13)
DPD_project\DPD_carri_maker_top.v (1532, 2014-03-20)
DPD_project\DPD_carri_maker_top.xst (1128, 2014-03-13)
DPD_project\DPD_carri_maker_top_envsettings.html (9498, 2014-03-20)
DPD_project\DPD_carri_maker_top_summary.html (4764, 2014-03-20)
DPD_project\DPD_carri_maker_top_xst.xrpt (11690, 2014-03-13)
DPD_project\DPD_carri_nco_counter.cmd_log (545, 2014-03-13)
DPD_project\DPD_carri_nco_counter.lso (6, 2014-03-13)
DPD_project\DPD_carri_nco_counter.ngc (1398, 2014-03-13)
DPD_project\DPD_carri_nco_counter.ngr (1068, 2014-03-13)
DPD_project\DPD_carri_nco_counter.prj (40, 2014-03-13)
DPD_project\DPD_carri_nco_counter.stx (0, 2014-03-13)
DPD_project\DPD_carri_nco_counter.syr (9258, 2014-03-13)
DPD_project\DPD_carri_nco_counter.tfi (172, 2014-03-13)
DPD_project\DPD_carri_nco_counter.v (1582, 2014-03-20)
DPD_project\DPD_carri_nco_counter.xst (1134, 2014-03-13)
DPD_project\DPD_carri_nco_counter_xst.xrpt (10543, 2014-03-13)
DPD_project\DPD_envl_mul2.cmd_log (237, 2014-03-20)
DPD_project\DPD_envl_mul2.lso (6, 2014-03-17)
DPD_project\DPD_envl_mul2.prj (32, 2014-03-17)
DPD_project\DPD_envl_mul2.stx (1694, 2014-03-17)
... ...
The following files were generated for 'fir_filter' in directory
E:\FPGA project\DPD_project\ipcore_dir\
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* fir_compiler_v6_2.mif
* fir_filter.mif
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* fir_filter.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* fir_filter.ngc
* fir_filter.v
* fir_filter.veo
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* fir_filter.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* fir_compiler_v6_2.mif
* fir_filter.asy
* fir_filter.mif
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* fir_filter.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* fir_filter_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* fir_filter.gise
* fir_filter.xise
Deliver Readme:
Readme file for the IP.
* fir_filter_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* fir_filter_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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