spdif_verilog
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:12KB
下载次数:137
上传日期:2014-04-29 14:13:26
上 传 者:
luregal
说明: 数字音频接口spdif ip core,verilog语言编写,带有testbench
(spdif verilog ip core)
文件列表:
debug_out_shifter.v (2754, 2010-02-25)
de_serialize.v (3635, 2010-02-25)
find_half_bit_width.v (1096, 2010-02-25)
find_preamble_length.v (2164, 2010-02-25)
find_sub_frame_width.v (849, 2010-02-25)
generic_fifo.v (1549, 2010-02-25)
lock_tracker.v (4657, 2010-02-25)
spdif_speed_detector.v (3825, 2010-02-25)
ss_capture_top.v (5623, 2010-02-25)
testbench_find_half_bit_width.v (1201, 2010-02-25)
testbench_find_preamble_length.v (2177, 2010-02-25)
testbench_lock_tracker.v (2790, 2010-02-25)
top_testbench.v (5758, 2010-02-25)
近期下载者:
相关文件:
收藏者: