OpenMIPS_VerilogHDL_Study_v1.1
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：430KB
下载次数：67
上传日期：2014-05-02 09:26:11
上 传 者：
薛定谔的喵
说明： 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！
(10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!)
文件列表:
OpenMIPS_VerilogHDL_Study_v1.1\min_sopc\data_ram.v (3324, 2014-02-23)
OpenMIPS_VerilogHDL_Study_v1.1\min_sopc\inst_rom.v (2339, 2014-02-07)
OpenMIPS_VerilogHDL_Study_v1.1\min_sopc\openmips_min_sopc.v (3253, 2014-03-09)
OpenMIPS_VerilogHDL_Study_v1.1\openmips模块连接关系图.vsd (651776, 2014-03-22)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\cp0_reg.v (6710, 2014-03-09)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\ctrl.v (3353, 2014-03-09)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\defines.v (7626, 2014-02-13)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\div.v (4942, 2014-03-02)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\ex.v (18536, 2014-03-16)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\ex_mem.v (6118, 2014-03-05)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\hilo_reg.v (2491, 2014-02-10)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\id.v (30587, 2014-03-15)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\id_ex.v (4948, 2014-03-02)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\if_id.v (2683, 2014-02-16)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\LLbit_reg.v (2494, 2014-03-07)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\mem.v (13672, 2014-03-16)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\mem_wb.v (4729, 2014-03-08)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\openmips.v (15914, 2014-03-14)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\pc_reg.v (2656, 2014-03-02)
OpenMIPS_VerilogHDL_Study_v1.1\rtl\regfile.v (3386, 2014-02-07)
OpenMIPS_VerilogHDL_Study_v1.1\testbench\openmips_min_sopc_tb.v (2330, 2014-02-16)
OpenMIPS_VerilogHDL_Study_v1.1\min_sopc (0, 2014-03-25)
OpenMIPS_VerilogHDL_Study_v1.1\rtl (0, 2014-03-25)
OpenMIPS_VerilogHDL_Study_v1.1\testbench (0, 2014-03-25)
OpenMIPS_VerilogHDL_Study_v1.1 (0, 2014-03-05)
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