文件列表:

.MySCMServerInfo (10973, 2010-09-09)
cstartup.s79 (4951, 2010-01-30)
thx.dep (136031, 2010-09-09)
thx.ewd (69695, 2010-03-27)
thx.ewp (184068, 2010-04-07)
thx_AT91SAM7L128.ewd (34780, 2010-01-30)
thx_AT91SAM7L128.ewp (99257, 2010-01-30)
txe_block_allocate.c (7867, 2010-01-30)
txe_block_pool_create.c (10159, 2010-01-30)
txe_block_pool_delete.c (7176, 2010-01-30)
txe_block_pool_info_get.c (7422, 2010-01-30)
txe_block_pool_prioritize.c (6422, 2010-01-30)
txe_block_release.c (6900, 2010-01-30)
txe_byte_allocate.c (8945, 2010-01-30)
txe_byte_pool_create.c (9876, 2010-01-30)
txe_byte_pool_delete.c (7534, 2010-01-30)
txe_byte_pool_info_get.c (7403, 2010-01-30)
txe_byte_pool_prioritize.c (6415, 2010-01-30)
txe_byte_release.c (7452, 2010-01-30)
txe_event_flags_create.c (9352, 2010-01-30)
txe_event_flags_delete.c (7236, 2010-01-30)
txe_event_flags_get.c (8529, 2010-01-30)
txe_event_flags_info_get.c (7629, 2010-01-30)
txe_event_flags_set.c (7129, 2010-01-30)
txe_event_flags_set_notify.c (6746, 2010-01-30)
txe_mutex_create.c (9485, 2010-01-30)
txe_mutex_delete.c (7154, 2010-01-30)
txe_mutex_get.c (8070, 2010-01-30)
txe_mutex_info_get.c (7468, 2010-01-30)
txe_mutex_prioritize.c (6373, 2010-01-30)
txe_mutex_put.c (7403, 2010-01-30)
txe_queue_create.c (10012, 2010-01-30)
txe_queue_delete.c (7059, 2010-01-30)
txe_queue_flush.c (6441, 2010-01-30)
txe_queue_front_send.c (7680, 2010-01-30)
txe_queue_info_get.c (7412, 2010-01-30)
txe_queue_prioritize.c (6316, 2010-01-30)
txe_queue_receive.c (7828, 2010-01-30)
... ...

Express Logic's ThreadX for ARM7 Thumb & 32-bit Mode Using the IAR 5 Tools 1. Installation ThreadX for the ARM7 is delivered on a single CD-ROM compatible disk. The entire distribution can be found in the sub-directory: \threadx To install ThreadX to your hard-disk, either run the supplied installer program Setup.exe or copy the distribution from the CD manually. To copy the ThreadX distribution manually, make a ThreadX directory on your hard-disk (we recommend c:\threadx\arm7\iar) and copy all the contents of the ThreadX sub-directory on the distribution disk. The following is an example MS-DOS copy command from the distribution directory (assuming source is d: and c: is your hard-drive): d:\threadx> xcopy /S *.* c:\threadx\arm7\iar 2. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the ThreadX workspace threadx.eww. Next, make the TX project the "active project" in the IAR Embedded Workbench and select the "Make" button. You should observe assembly and compilation of a series of ThreadX source files. This results in the ThreadX run-time library file tx.a, which is needed by the application. 3. Demonstration System The ThreadX demonstration is designed to execute under the IAR Windows-based ARM7 simulator. Building the demonstration is easy; simply make the demo_threadx.ewp project the "active project" in the IAR Embedded Workbench and select the "Make" button. You should observe the compilation of demo_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file demo_threadx.d79 is a binary file that can be downloaded and executed on IAR's ARM7 simulator. A SPECIAL NOTE: The IAR ARM simulator does simulate interrupts. In order for the ThreadX demonstration to run properly, a periodic IRQ interrupt must be setup in the IAR debugging environment. We recommend setting an IRQ interrupt to execute every 9999 cycles. 4. System Initialization The entry point in ThreadX for the ARM7 using IAR tools is at label ?cstartup. This is defined within the IAR compiler's startup code. In addition, this is where all static and global preset C variable initialization processing takes place. The ThreadX tx_initialize_low_level.s79 file is responsible for setting up various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s79, which is a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s79 also determines the first available address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. To accomplish this, a section is created in tx_initialize_low_level.s79 called FREE_MEM, which must be located after all other RAM sections in memory. 5. Register Usage and Stack Frames The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch registers for each function. All other registers used by a C function must be preserved by the function. ThreadX takes advantage of this in situations where a context switch happens as a result of making a ThreadX service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Interrupted Stack Frame Non-Interrupt Stack Frame 0x00 1 0 0x04 CPSR CPSR 0x08 r0 (a1) r4 (v1) 0x0C r1 (a2) r5 (v2) 0x10 r2 (a3) r6 (v3) 0x14 r3 (a4) r7 (v4) 0x18 r4 (v1) r8 (v5) 0x1C r5 (v2) r9 (v6) 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) 0x2C r9 (v6) 0x30 r10 (v7) 0x34 r11 (fp) 0x38 r12 (ip) 0x3C r14 (lr) 0x40 PC 6. Conditional Compilation Switches The following are conditional compilation options for building the ThreadX library and application: TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ nested support. If IRQ nested interrupt support is needed, this define should be applied to tx_initialize_low_level.s79. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ nested support. If FIQ nested interrupt support is needed, this define should be applied to tx_initialize_low_level.s79. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see Chapter 2 in the "ThreadX User Guide" for more details. TX_MAX_PRIORITIES Defines the priority levels for ThreadX. Legal values range from 32 through 1024 (inclusive) and MUST be evenly divisible by 32. Increasing the number of priority levels supported increases the RAM usage by 128 bytes for every group of 32 priorities. However, there is only a negligible effect on performance. By default, this value is set to 32 priority levels. TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is used for error checking when threads are created. The default value is port-specific and is found in tx_port.h. TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal ThreadX timer thread. This thread processes all thread sleep requests as well as all service call timeouts. In addition, all application timer callback routines are invoked from this context. The default value is port-specific and is found in tx_port.h. TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer thread. The default value is priority 0 - the highest priority in ThreadX. The default value is defined in tx_port.h. TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system timer thread for ThreadX. This results in improved performance on timer events and smaller RAM requirements because the timer stack and control block are no longer needed. However, using this option moves all the timer expiration processing to the timer ISR level. By default, this option is not defined. TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX timers in-line instead of using a function call. This improves performance but slightly increases code size. By default, this option is not defined. TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each thread's stack is disabled. By default, this option is not defined. TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, which includes analysis of how much stack has been used and examination of data pattern "fences" before and after the stack area. If a stack error is detected, the registered application stack error handler is called. This option does result in slightly increased overhead and code size. Please review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature and slightly reduces code size and improves performance. Of course, the preemption-threshold capabilities are no longer available. By default, this option is not defined. TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX global C data structures to zero. This should only be used if the compiler's initialization code sets all un-initialized C global data to zero. Using this option slightly reduces code size and improves performance during initialization. By default, this option is not defined. TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various ThreadX objects. Using this option slightly reduces code size and improves performance. TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on block pools. By default, this option is not defined. TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on byte pools. By default, this option is not defined. TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on event flags groups. By default, this option is not defined. TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on mutexes. By default, this option is not defined. TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on queues. By default, this option is not defined. TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on semaphores. By default, this option is not defined. TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on threads. By default, this option is not defined. TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace time-stamp source defined previously. If the time-stamp source is 16-bits, this value should be 0xFFFF. Alternatively, if the time-stamp source is 32-bits, this value should be 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence in assembly files, to ensure correct operation on systems that use both ARM and Thumb mode. By default, this option is not defined 7. Improving Performance The distribution version of ThreadX is built without any compiler optimizations. This makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. In addition, you can eliminate the ThreadX basic API error checking by compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING defined. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM7 targets. There are a certain set of requirements that are defined in the following sub-sections: 8.1 Vector Area The ARM7 vectors start at address zero. The demonstration system startup cstartup.s79 file contains the vectors and is loaded at address zero. On actual hardware platforms, this area might have to be copied to address 0. 8.2 IRQ ISRs ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 8.2.1 Standard IRQ ISRs The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s79: PUBLIC __tx_irq_handler PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ B _tx_thread_context_save __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; ; /* Application ISR dispatch call goes here! */ ; ; /* Jump to context restore to restore system context. */ B _tx_thread_context_restore 8.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s79: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_example_vectored_irq_handler __tx_example_vectored_irq_handler ; ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available f ... ...

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