jtag_memory_v0.12
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：12784KB
下载次数：14
上传日期：2014-05-11 09:57:28
上 传 者：
sik
说明： JTAG调试接口与testbench，附加memory模块并支持cpu和wishbone
(JTAG TAP with Controller and testbench ,and an addition of block memory and the potential support of cpu and wishbone)
文件列表:
jtag_memory_v0.12 (0, 2014-04-24)
jtag_memory_v0.12\.lso (6, 2014-03-18)
jtag_memory_v0.12\_ngo (0, 2014-04-24)
jtag_memory_v0.12\_ngo\cs_icon_pro (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg7B\dbg__if.bin (29097, 2014-03-18)
jtag_memory_v0.12\xst\work\vlg7B (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg78\dbg__cpu.bin (61914, 2014-02-19)
jtag_memory_v0.12\xst\work\vlg78 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg73\dbg__cpu__registers.bin (7347, 2014-02-19)
jtag_memory_v0.12\_ngo\cs_icon_pro\generate_icon_pro.xco (681, 2014-04-09)
jtag_memory_v0.12\xst\work\vlg73 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg72\rd2048x32mux16.bin (55958, 2014-02-19)
jtag_memory_v0.12\xst\work\vlg72 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg70\core2048x32.bin (2039, 2014-03-18)
jtag_memory_v0.12\xst\work\vlg70 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg6B\clk__gen.bin (1983, 2014-03-18)
jtag_memory_v0.12\xst\work\vlg6B (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg69\led.bin (2802, 2014-02-20)
jtag_memory_v0.12\xst\work\vlg69 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg52\ram__4c.bin (10481, 2014-03-18)
jtag_memory_v0.12\xst\work\vlg52 (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg4E\jtag__tap.bin (28750, 2014-03-18)
jtag_memory_v0.12\_ngo\cs_ila_pro_0 (0, 2014-04-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\_xmsgs (0, 2014-04-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\_xmsgs\xst.xmsgs (64509, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\coregen.cgc (43289, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\coregen.cgp (518, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\coregen.log (1636, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\generate_ila_pro_0.xco (3126, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.cdc (975, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.gise (1169, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.vhd (1021, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.vho (1474, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.xco (4127, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0.xise (40266, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0_flist.txt (210, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\ila_pro_0_xmdf.tcl (2521, 2014-02-24)
jtag_memory_v0.12\_ngo\cs_ila_pro_0\tmp (0, 2014-04-24)
jtag_memory_v0.12\xst\work\vlg4E (0, 2014-04-24)
... ...
The following files were generated for 'icon_pro' in directory
E:\Chaoxing\jtag_memory_v0.1\jtag_memory_v0.12\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：