MATLABaFPGA

所属分类:matlab编程
开发工具:matlab
文件大小:14084KB
下载次数:75
上传日期:2014-05-15 16:22:26
上 传 者马岳
说明:  《数字通信同步技术的MATLAB与FPGA实现》配套程序
(" Synchronous digital communication MATLAB and FPGA technology to achieve" matching program)

文件列表:
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\.recordref (0, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\layer0.sro (2338, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\layer0.tlg (85, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\lec\SymbExam.vlc (73, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\lec\SymbExam.vmc (82, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\lec\SymbExam.vsc (100, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\pepExtractor.prj (19, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\rpt_SymbExam.areasrr (2045, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\stderr.log (0, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\stdout.log (602, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.edn (11448, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.fse (0, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.gise (7219, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.ise (53472, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.ncf (246, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.prj (1851, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.sdc (0, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.srd (4632, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.srm (6570, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.srr (5576, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.srs (1349, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.vhd (441, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.vtc (1777, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam.xise (41131, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_compile.tcl (18, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_map.tcl (14, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_open_file.tcl (52, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\version (138, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject (41, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject_StrTbl (21, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl (27, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl_StrTbl (3817, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main (25, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main_StrTbl (10, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CSourceProcessView (59, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CSourceProcessView_StrTbl (10, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector (27, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector_StrTbl (33, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly (74, 2013-03-18)
数字通信同步技术的MATLAB与FPGA实现\SyncPrograms\Chapter_2\E2_1_SymbExam\SymbExam_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly_StrTbl (55, 2013-03-18)
... ...

The following files were generated for in directory D:\SyncPrograms\Chapter_7\E7_1_BitSync\BitSync: sin.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. sin.edn: Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx (R) FPGA. sin.sym: Please see the core data sheet. sin.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. sin.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. sin.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. sin.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. sin.xco: CORE Generator input file containing the parameters used to regenerate a core. sin_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. sin_readme.txt: Text file indicating the files generated and how they are used. sin_SINCOS_TABLE_TRIG_ROM.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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