rs(63-45)
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：15KB
下载次数：11
上传日期：2014-05-23 17:38:31
上 传 者：
julianaisme
说明： 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。
(VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.)
文件列表:
rs(63,45) (0, 2014-05-23)
rs(63,45)\RS.vhd (7006, 2014-05-12)
rs(63,45)\mula_0.vhd (1118, 2014-03-28)
rs(63,45)\mula_11.vhd (1194, 2014-03-27)
rs(63,45)\mula_21.vhd (1239, 2014-03-28)
rs(63,45)\mula_22.vhd (1221, 2014-03-28)
rs(63,45)\mula_25.vhd (1230, 2014-03-27)
rs(63,45)\mula_3.vhd (1143, 2014-03-27)
rs(63,45)\mula_31.vhd (1203, 2014-03-27)
rs(63,45)\mula_32.vhd (1203, 2014-03-27)
rs(63,45)\mula_35.vhd (1266, 2014-03-27)
rs(63,45)\mula_38.vhd (1304, 2014-03-28)
rs(63,45)\mula_45.vhd (1234, 2013-12-20)
rs(63,45)\mula_48.vhd (1230, 2014-03-11)
rs(63,45)\mula_51.vhd (1273, 2014-03-28)
rs(63,45)\mula_59.vhd (1212, 2014-03-27)
rs(63,45)\mula_6.vhd (1181, 2014-03-27)
rs(63,45)\mula_61.vhd (1153, 2014-03-28)
rs(63,45)\rscode.vhd (6523, 2014-03-31)
rs(63,45)\rstest.vhd (3900, 2014-04-19)
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