MIPSCPU

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:166KB
下载次数:48
上传日期:2014-05-26 02:25:33
上 传 者zhql945
说明:  这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过
(This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by)

文件列表:
12061115_周其林.docx (38060, 2013-12-28)
Project6(finish)\alu.v (1495, 2013-12-27)
Project6(finish)\be_load.v (747, 2013-12-27)
Project6(finish)\be_save.v (496, 2013-12-27)
Project6(finish)\code.txt (1190, 2013-12-22)
Project6(finish)\controller.v (5539, 2013-12-27)
Project6(finish)\dm.v (2180, 2013-12-27)
Project6(finish)\ext.v (202, 2013-12-27)
Project6(finish)\gpr.v (614, 2013-12-27)
Project6(finish)\head_mips.v (2456, 2013-12-27)
Project6(finish)\im.v (422, 2013-12-27)
Project6(finish)\mips.cr.mti (3158, 2013-12-28)
Project6(finish)\mips.mpf (86161, 2013-12-28)
Project6(finish)\mips.v (1611, 2013-12-27)
Project6(finish)\mux.v (581, 2013-12-27)
Project6(finish)\npc.v (825, 2013-12-27)
Project6(finish)\pc.v (350, 2013-12-27)
Project6(finish)\testbench.v (197, 2013-12-27)
Project6(finish)\vsim.wlf (98304, 2013-12-27)
Project6(finish)\wave1.bmp (2051118, 2013-12-27)
Project6(finish)\wave2.bmp (2051118, 2013-12-27)
Project6(finish)\work\alu\verilog.asm64 (48464, 2013-12-27)
Project6(finish)\work\alu\verilog.rw64 (1024, 2013-12-27)
Project6(finish)\work\alu\_primary.dat (1588, 2013-12-27)
Project6(finish)\work\alu\_primary.dbs (2734, 2013-12-27)
Project6(finish)\work\alu\_primary.vhd (802, 2013-12-27)
Project6(finish)\work\be_load\verilog.asm64 (24816, 2013-12-27)
Project6(finish)\work\be_load\verilog.rw64 (400, 2013-12-27)
Project6(finish)\work\be_load\_primary.dat (1082, 2013-12-27)
Project6(finish)\work\be_load\_primary.dbs (1131, 2013-12-27)
Project6(finish)\work\be_load\_primary.vhd (429, 2013-12-27)
Project6(finish)\work\be_save\verilog.asm64 (15392, 2013-12-27)
Project6(finish)\work\be_save\verilog.rw64 (314, 2013-12-27)
Project6(finish)\work\be_save\_primary.dat (690, 2013-12-27)
Project6(finish)\work\be_save\_primary.dbs (739, 2013-12-27)
Project6(finish)\work\be_save\_primary.vhd (343, 2013-12-27)
Project6(finish)\work\controller\verilog.asm64 (137888, 2013-12-27)
Project6(finish)\work\controller\verilog.rw64 (2991, 2013-12-27)
Project6(finish)\work\controller\_primary.dat (7469, 2013-12-27)
Project6(finish)\work\controller\_primary.dbs (23574, 2013-12-27)
... ...

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