phyjingjian
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5032KB
下载次数：154
上传日期：2014-07-01 23:27:31
上 传 者：
bsqxsw
说明： 通过fpga对phy芯片88e1111进行控制，可改变工作模式，传输速度等。
(By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.)
文件列表:
phyjingjian (0, 2013-12-19)
phyjingjian\.lso (6, 2012-12-11)
phyjingjian\1.cpj (59245, 2012-12-11)
phyjingjian\PHY_Management.cmd_log (822, 2012-12-11)
phyjingjian\PHY_Management.lso (6, 2012-12-11)
phyjingjian\PHY_Management.ngc (1979, 2012-12-11)
phyjingjian\PHY_Management.ngr (1800, 2012-12-11)
phyjingjian\PHY_Management.prj (25, 2012-12-11)
phyjingjian\PHY_Management.stx (1207, 2012-12-11)
phyjingjian\PHY_Management.syr (15863, 2012-12-11)
phyjingjian\PHY_Management.tfi (159, 2012-12-11)
phyjingjian\PHY_Management.xst (182, 2012-12-11)
phyjingjian\PHY_Management_envsettings.html (9390, 2012-12-11)
phyjingjian\PHY_Management_isim_beh.exe (94720, 2012-12-11)
phyjingjian\PHY_Management_isim_beh1.wdb (4451, 2012-12-11)
phyjingjian\PHY_Management_stx_beh.prj (97, 2012-12-11)
phyjingjian\PHY_Management_summary.html (5638, 2012-12-11)
phyjingjian\PHY_Management_xst.xrpt (12971, 2012-12-11)
phyjingjian\PHY_PIN.ucf (243, 2012-12-05)
phyjingjian\TEST_top.v (1083, 2012-12-11)
phyjingjian\TEST_top_stx_beh.prj (187, 2012-12-11)
phyjingjian\_ngo (0, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro (0, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\_xmsgs (0, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\_xmsgs\netgen.xmsgs (651, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\_xmsgs\xst.xmsgs (127838, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\coregen.cgc (15555, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\coregen.cgp (518, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\coregen.log (1837, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\generate_icon_pro.xco (651, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.ejp (1557, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.gise (1167, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.vhd (43637, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.vho (1303, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.xco (1397, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro.xise (40118, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro_flist.txt (199, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\icon_pro_xmdf.tcl (2519, 2012-12-11)
phyjingjian\_ngo\cs_icon_pro\tmp (0, 2012-12-11)
... ...
The following files were generated for 'icon_pro' in directory
D:\FPGA_design\phy jingjian\phyjingjian\_ngo\cs_icon_pro\
icon_pro.ejp:
Please see the core data sheet.
icon_pro.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
icon_pro.vhd:
Unisim VHDL file containing the information required to simulate
the module.
icon_pro.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
icon_pro.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
icon_pro.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro_readme.txt:
Text file indicating the files generated and how they are used.
icon_pro_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
icon_pro_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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