UART-Verilog-source
所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:3KB
下载次数:8
上传日期:2014-07-08 09:28:37
上 传 者:
chai891102
说明: Verilog编写UART串口例程,实现FPGA与上位机串口通信,利用ASCII码进行大小写转换,在Xilinx Virtex-5开发板测试通过
(UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test)
文件列表:
baud.v (368, 2013-06-22)
GenesysGeneral.ucf (1371, 2013-07-03)
uart.v (897, 2013-06-29)
uart_dataprocess.v (1256, 2013-06-23)
uart_rec.v (1475, 2013-06-23)
uart_tb.v (990, 2013-07-06)
uart_tra.v (1752, 2013-06-23)
近期下载者:
相关文件:
收藏者: