code
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：161KB
下载次数：32
上传日期：2014-08-18 03:20:21
上 传 者：
yjw_yang
说明： Mips单周期CPU设计（支持7条指令addu、subu、ori、lw、sw、beq、lui）
(Mips single-cycle CPU design)
文件列表:
code\ALU.v (324, 2014-04-04)
code\ALU.v.bak (324, 2014-04-04)
code\code.bak (2, 2014-04-03)
code\code.txt (390, 2014-04-04)
code\Ctl.v (603, 2014-04-16)
code\Ctl.v.bak (620, 2014-04-16)
code\datapath.v (923, 2014-04-04)
code\datapath.v.bak (928, 2014-04-03)
code\dm.v (367, 2014-04-01)
code\dm.v.bak (365, 2014-04-01)
code\ext.v (139, 2014-04-02)
code\ext.v.bak (124, 2014-04-02)
code\GPR.v (536, 2014-04-01)
code\GPR.v.bak (2, 2014-04-01)
code\head.v (365, 2014-04-16)
code\head.v.bak (115, 2014-04-02)
code\im.v (217, 2014-04-03)
code\im.v.bak (218, 2014-04-03)
code\mips.v (608, 2014-04-04)
code\mips.v.bak (617, 2014-04-04)
code\Mux.v (481, 2014-04-04)
code\Mux.v.bak (481, 2014-04-02)
code\PC.v (237, 2014-04-03)
code\PC.v.bak (220, 2014-04-02)
code\PC_a.v (34, 2014-04-02)
code\PC_a.v.bak (2, 2014-04-02)
code\PC_count.v (228, 2014-04-04)
code\PC_count.v.bak (227, 2014-04-04)
code\project3.cr.mti (2, 2014-04-01)
code\project_3.cr.mti (3252, 2014-04-04)
code\project_3.mpf (93079, 2014-04-04)
code\tcl_stacktrace.txt (1412, 2014-04-03)
code\testbench.v (664, 2014-04-04)
code\testbench.v.bak (669, 2014-04-04)
code\testbench_ctr.v (770, 2014-04-02)
code\testbench_ctr.v.bak (770, 2014-04-02)
code\top.v (453, 2014-04-03)
code\top.v.bak (422, 2014-04-03)
code\vsim.wlf (983040, 2014-04-04)
code\vsim_stacktrace.vstf (736, 2014-04-04)
... ...
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