sobel
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:6109KB
下载次数:99
上传日期:2014-09-11 15:31:17
上 传 者:
zhou hui
说明: 在FPGA中,采用verilog HDL语言实现图像处理算法sobel,仿真实验通过
(In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment)
文件列表:
sobel (0, 2014-08-27)
sobel\abs.bmm (0, 2014-08-26)
sobel\data3by3.v (3321, 2014-08-26)
sobel\data3by3_compute.gise (16633, 2014-08-27)
sobel\data3by3_compute.xise (41504, 2014-08-27)
sobel\data_grads.v (3158, 2014-08-27)
sobel\fuse.log (3932, 2014-08-27)
sobel\fuse.xmsgs (1970, 2014-08-27)
sobel\fuseRelaunch.cmd (228, 2014-08-27)
sobel\generate_data3by3.v (2328, 2014-08-26)
sobel\generate_data3by3_summary.html (3558, 2014-08-26)
sobel\Grads.bld (991, 2014-08-26)
sobel\Grads.cmd_log (7023, 2014-08-27)
sobel\Grads.lso (6, 2014-08-27)
sobel\Grads.ncd (102790, 2014-08-26)
sobel\Grads.ngc (67303, 2014-08-27)
sobel\Grads.ngd (189365, 2014-08-26)
sobel\Grads.ngr (78812, 2014-08-27)
sobel\Grads.pad (14425, 2014-08-26)
sobel\Grads.par (7906, 2014-08-26)
sobel\Grads.pcf (217, 2014-08-26)
sobel\Grads.prj (440, 2014-08-27)
sobel\Grads.ptwx (17226, 2014-08-26)
sobel\Grads.stx (0, 2014-08-27)
sobel\Grads.syr (28466, 2014-08-27)
sobel\Grads.twr (6069, 2014-08-26)
sobel\Grads.twx (25189, 2014-08-26)
sobel\Grads.unroutes (155, 2014-08-26)
sobel\grads.v (2152, 2014-08-27)
sobel\Grads.xpi (46, 2014-08-26)
sobel\Grads.xst (1087, 2014-08-27)
sobel\Grads_envsettings.html (15996, 2014-08-27)
sobel\Grads_guide.ncd (102790, 2014-08-26)
sobel\Grads_map.map (6837, 2014-08-26)
sobel\Grads_map.mrp (18600, 2014-08-26)
sobel\Grads_map.ncd (56302, 2014-08-26)
sobel\Grads_map.ngm (357511, 2014-08-26)
sobel\Grads_map.xrpt (32146, 2014-08-26)
sobel\Grads_ngdbuild.xrpt (12341, 2014-08-26)
sobel\Grads_pad.csv (14457, 2014-08-26)
... ...
The following files were generated for 'sqr' in directory
E:\mywork\sobel\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* sqr.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* sqr.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* sqr.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* sqr.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* sqr.v
All Documents Generator:
Please see the core data sheet.
* sqr/doc/cordic_ds249.pdf
* sqr/doc/cordic_v4_0_vinfo.html
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* sqr.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* sqr.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* sqr_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* _xmsgs/pn_parser.xmsgs
* sqr.gise
* sqr.xise
Deliver Readme:
Readme file for the IP.
* sqr_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* sqr_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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