rgmiitest

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1671KB
下载次数:104
上传日期:2014-10-16 10:58:33
上 传 者hqxyy
说明:  rgmii接口实现ip,源码里面包括了rgmii接口,还有完整的测试程序
(rgmii interface relization code,including rgmii ip and the test function)

文件列表:
rgmiitest (0, 2014-08-19)
rgmiitest\doc (0, 2014-08-19)
rgmiitest\doc\tri_mode_eth_mac_ds297.pdf (497376, 2014-08-19)
rgmiitest\doc\tri_mode_eth_mac_gsg139.pdf (385136, 2014-08-19)
rgmiitest\doc\tri_mode_eth_mac_ug138.pdf (1541637, 2014-08-19)
rgmiitest\example_design (0, 2014-08-19)
rgmiitest\example_design\address_swap_module.v (14526, 2014-08-19)
rgmiitest\example_design\address_swap_module.vhd (13953, 2014-08-19)
rgmiitest\example_design\clk_gen.v (4040, 2014-08-19)
rgmiitest\example_design\clk_gen.vhd (4291, 2014-08-19)
rgmiitest\example_design\clk_pack.vhd (4061, 2014-08-19)
rgmiitest\example_design\fifo (0, 2014-08-19)
rgmiitest\example_design\fifo\rx_client_fifo.v (30886, 2014-08-19)
rgmiitest\example_design\fifo\rx_client_fifo.vhd (35271, 2014-08-19)
rgmiitest\example_design\fifo\ten_100_1g_eth_fifo.v (7999, 2014-08-19)
rgmiitest\example_design\fifo\ten_100_1g_eth_fifo.vhd (9721, 2014-08-19)
rgmiitest\example_design\fifo\tx_client_fifo.v (44895, 2014-08-19)
rgmiitest\example_design\fifo\tx_client_fifo.vhd (52771, 2014-08-19)
rgmiitest\example_design\johnson_cntr.v (4163, 2014-08-19)
rgmiitest\example_design\johnson_cntr.vhd (5851, 2014-08-19)
rgmiitest\example_design\physical (0, 2014-08-19)
rgmiitest\example_design\physical\rgmii_v2_0_if.v (15643, 2014-08-19)
rgmiitest\example_design\physical\rgmii_v2_0_if.vhd (15259, 2014-08-19)
rgmiitest\example_design\rgmiitest_block.v (14641, 2014-08-19)
rgmiitest\example_design\rgmiitest_block.vhd (21354, 2014-08-19)
rgmiitest\example_design\rgmiitest_example_design.ucf (93, 2014-08-19)
rgmiitest\example_design\rgmiitest_example_design.v (18067, 2014-08-19)
rgmiitest\example_design\rgmiitest_example_design.vhd (21120, 2014-08-19)
rgmiitest\example_design\rgmiitest_locallink.v (14423, 2014-08-19)
rgmiitest\example_design\rgmiitest_locallink.vhd (20583, 2014-08-19)
rgmiitest\example_design\rgmiitest_mod.v (4579, 2014-08-19)
rgmiitest\example_design\rx_clk_gen.v (9084, 2014-08-19)
rgmiitest\example_design\rx_clk_gen.vhd (10206, 2014-08-19)
rgmiitest\example_design\tx_clk_gen.v (6724, 2014-08-19)
rgmiitest\example_design\tx_clk_gen.vhd (8083, 2014-08-19)
rgmiitest\simulation (0, 2014-08-19)
rgmiitest\simulation\demo_tb.v (66295, 2014-08-19)
rgmiitest\simulation\demo_tb.vhd (65395, 2014-08-19)
rgmiitest\simulation\functional (0, 2014-08-19)
rgmiitest\simulation\functional\simulate_mti.do (924, 2014-08-19)
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Core Name: Xilinx Tri-Mode Ethernet MAC Version: 3.5 Release Date: March 24, 2008 ================================================================================ This document contains the following sections: 1. Introduction 2. New Features 3. Resolved Issues 4. Known Issues 5. Technical Support 6. Other Information 7. Core Release History ================================================================================ 1. INTRODUCTION For the most recent updates to the IP installation instructions for this core, please go to: http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm For system requirements: http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm This file contains release notes for the Xilinx LogiCORE Tri-Mode Ethernet MAC v3.5 solution. For the latest core updates, see the product page at: www.xilinx.com/products/ipcenter/TEMAC.htm 2. NEW FEATURES - ISE 10.1i software support - Virtex-5 FXT support - VCS simulator support - Added support for control frames >= *** bytes 3. RESOLVED ISSUES - Incorrect data can be read out of the RX LL FIFO if rd_dst_rdy_n has been de-asserted - See AR #29660 - A pipelined version of the frame_in_fifo signal is now used to ensure valid frame data - Missing period constraint on rx_clock added. - This may affect some families implementing GMII. - CR #456603 Missing RX CLK constraint for GMII (subset of families) 4. KNOWN ISSUES The following are known issues for v3.5 of this core at time of release: - None The most recent information, including known issues, workarounds, and resolutions for this version is provided in the release notes Answer Record for the ISE 10.1i IP Update at <<>> 5. TECHNICAL SUPPORT To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 6. OTHER INFORMATION 7. CORE RELEASE HISTORY Date By Version Change Description ======================================================================== 03/2008 Xilinx, Inc. 3.5 Release for ISE 10.1i 08/2007 Xilinx, Inc. 3.4 Release for ISE 9.2i 04/2007 Xilinx, Inc. 3.3 rev 1 Spartan(TM)-3A DSP support 02/2007 Xilinx, Inc. 3.3 Release for ISE 9.1i 09/2006 Xilinx, Inc. 3.2 Release for ISE 8.2i 07/2006 Xilinx, Inc. 3.1 Release for ISE 8.2i 01/2006 Xilinx, Inc. 2.2 Release for ISE 8.1i 06/2005 Xilinx, Inc. 2.1 patch 1 Patch release 04/2005 Xilinx, Inc. 2.1 Release for ISE 7.1i 09/2004 Xilinx, Inc. 1.1 Release for ISE 6.3i ======================================================================== (c) 2004-2008 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

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