usb

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:3053KB
下载次数:41
上传日期:2014-10-20 15:43:28
上 传 者callmemaybe
说明:  pc与fpga之间的数据传输 在fpga上有一个usb芯片cy68013 用verilog来对usb芯片进行控制
(the communication between pc and the fpga,these is a cy68013 on the fpga,which is controled through verilog)

文件列表:
usb\USB_LOOP_TEST_du\fuse.log (1395, 2012-11-23)
usb\USB_LOOP_TEST_du\fuse.xmsgs (592, 2012-11-23)
usb\USB_LOOP_TEST_du\fuseRelaunch.cmd (271, 2012-11-23)
usb\USB_LOOP_TEST_du\iseconfig\USB_LOOP_TEST.projectmgr (9584, 2014-10-13)
usb\USB_LOOP_TEST_du\iseconfig\USB_LOOP_TEST.xreport (21284, 2014-10-13)
usb\USB_LOOP_TEST_du\isim\isim_usage_statistics.html (1670, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\pn_info (6, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\isimcrash.log (0, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg (6612, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\isimkernel.log (566, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\netId.dat (108, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\tmp_save\_1 (3419, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\USB_LOOP_Sim_isim_beh.exe (29506, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000000707116053_0133064148.c (4373, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000000707116053_0133064148.didat (4528, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000000707116053_0133064148.nt.obj (2631, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000002070202119_3714852992.c (30543, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000002070202119_3714852992.didat (5388, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000002070202119_3714852992.nt.obj (9275, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.c (7967, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.didat (5408, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.nt.obj (3134, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\USB_LOOP_Sim_isim_beh.exe_main.c (1353, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_Sim_isim_beh.exe.sim\work\USB_LOOP_Sim_isim_beh.exe_main.nt.obj (1273, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\isimcrash.log (0, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg (5503, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\isimkernel.log (569, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\netId.dat (204, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\tmp_save\_1 (2577, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\USB_LOOP_TEST_isim_beh.exe (28051, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000000115889670_3714852992.c (30784, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000000115889670_3714852992.didat (5392, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000000115889670_3714852992.nt.obj (9479, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.c (7968, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.didat (5412, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.nt.obj (3134, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\USB_LOOP_TEST_isim_beh.exe_main.c (1301, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\USB_LOOP_TEST_isim_beh.exe.sim\work\USB_LOOP_TEST_isim_beh.exe_main.nt.obj (1185, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\work\@u@s@b_@l@o@o@p_@sim.sdb (2945, 2012-11-23)
usb\USB_LOOP_TEST_du\isim\work\@u@s@b_@l@o@o@p_@t@e@s@t.sdb (7185, 2012-11-23)
... ...

The following files were generated for 'icon_pro' in directory E:\zhongjie\USB_LOOP_TEST\_ngo\cs_icon_pro\ icon_pro.ejp: Please see the core data sheet. icon_pro.gise: ISE Project Navigator support file. This is a generated file and should not be edited directly. icon_pro.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. icon_pro.vhd: Unisim VHDL file containing the information required to simulate the module. icon_pro.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. icon_pro.xco: CORE Generator input file containing the parameters used to regenerate a core. icon_pro.xise: ISE Project Navigator support file. This is a generated file and should not be edited directly. icon_pro_readme.txt: Text file indicating the files generated and how they are used. icon_pro_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. icon_pro_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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