Crazy_FPGA_Examples
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9481KB
下载次数：35
上传日期：2014-10-22 23:02:39
上 传 者：
cyx0610
说明： crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。
(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)
文件列表:
Crazy_FPGA_Examples\01_Counter_Design\dev\Counter_Design.qpf (1281, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\Counter_Design.qsf (3178, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\Counter_Design.qws (2203, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.asm.rpt (7503, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.done (26, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.fit.rpt (125908, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.fit.smsg (703, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.fit.summary (624, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.flow.rpt (6762, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.jdi (233, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.map.rpt (21036, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.map.summary (477, 2014-05-19)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.pin (33017, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.sof (496867, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.sta.rpt (79720, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\output_files\Counter_Design.sta.summary (934, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\VIP_System.sdc (2393, 2014-04-22)
Crazy_FPGA_Examples\01_Counter_Design\dev\VIP_System.sdc.bak (2396, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\Counter_Design.v (1701, 2013-10-21)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\Counter_Design_TB.cr.mti (695, 2014-07-03)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\Counter_Design_TB.mpf (20229, 2014-07-03)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\Counter_Design_TB.v (2205, 2013-10-24)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\transcript (210, 2014-07-03)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\vsim.wlf (73728, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\vsim_stacktrace.vstf (960, 2013-10-21)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\wave.do (1145, 2013-10-21)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design\verilog.prw (187, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design\verilog.psm (3056, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design\_primary.dat (377, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design\_primary.dbs (424, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design\_primary.vhd (252, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design_@t@b\verilog.prw (526, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design_@t@b\verilog.psm (6752, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design_@t@b\_primary.dat (633, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design_@t@b\_primary.dbs (877, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\@counter_@design_@t@b\_primary.vhd (94, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\_info (1347, 2014-04-10)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\_temp\vlog19ssna (395, 2013-10-21)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\_temp\vlog2zrsty (395, 2013-10-21)
Crazy_FPGA_Examples\01_Counter_Design\sim\Counter_Design_TB\work\_temp\vlogik2gwb (396, 2013-10-21)
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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