myfpga
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6113KB
下载次数：5
上传日期：2014-11-06 13:18:38
上 传 者：
_shangguan_
说明： 详细描述设计过程
① 指令格式设计
② 微操作的定义
③ 节拍的划分
④ 处理器详细结构设计框图及功能描述(评分重点)
a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及.
b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上
⑤ 各功能模块结构设计框图及功能描述（评分重点）
⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义）
⑦ 实验总结，在调试和下载过程中遇到的问题
(Design Process Design ② ① instruction format defined micro-operation ③ ④ processor division beat a detailed description of the structural design and function block diagram (score focus) a detailed description single wire connection between modules with thin lines, 2 and above with crude line and mark the number and. b. Use the arrow indicating the flow of data, signal names used in cases of functional modules shall be marked ⑤ structural design diagram and functional description (score focus) ⑥ VHDL code on connection, UCF file test instruction sequence (the meaning of each instruction) ⑦ experiments summarized in debugging and downloading problems encountered in the process)
文件列表:
myfpga\MCPU\MALU.vhd (2232, 2011-11-28)
myfpga\MCPU\MBACK.vhd (1372, 2011-11-03)
myfpga\MCPU\MCLK.vhd (726, 2011-11-01)
myfpga\MCPU\MCPU.cmd_log (78, 2011-12-04)
myfpga\MCPU\MCPU.ise (265974, 2011-12-04)
myfpga\MCPU\MCPU.ise_ISE_Backup (265974, 2011-12-04)
myfpga\MCPU\MCPU.lso (6, 2011-12-04)
myfpga\MCPU\MCPU.ngc (127750, 2011-12-04)
myfpga\MCPU\MCPU.ngr (255858, 2011-12-04)
myfpga\MCPU\MCPU.prj (158, 2011-12-04)
myfpga\MCPU\MCPU.stx (0, 2011-12-04)
myfpga\MCPU\MCPU.syr (58384, 2011-12-04)
myfpga\MCPU\MCPU.vhd (4693, 2011-11-28)
myfpga\MCPU\MCPU.xst (1134, 2011-12-04)
myfpga\MCPU\MCPU_summary.html (3530, 2011-12-04)
myfpga\MCPU\MCPU_vhdl.prj (263, 2011-12-04)
myfpga\MCPU\MCTRL.vhd (1555, 2011-11-28)
myfpga\MCPU\MGETIR.vhd (1029, 2011-11-10)
myfpga\MCPU\MMEM.vhd (928, 2011-11-06)
myfpga\MCPU\MyALU.jhd (44, 2011-12-04)
myfpga\MCPU\MyALU.tbw (492, 2011-11-28)
myfpga\MCPU\MyALU_bencher.prj (22, 2011-12-04)
myfpga\MCPU\MyBACK.jhd (46, 2011-12-04)
myfpga\MCPU\MyBACK.tbw (500, 2011-11-08)
myfpga\MCPU\MyCLK.jhd (44, 2011-12-04)
myfpga\MCPU\MyCLK.tbw (541, 2011-11-28)
myfpga\MCPU\MyCPU.jhd (44, 2011-12-04)
myfpga\MCPU\MyCPU.tbw (874, 2011-11-28)
myfpga\MCPU\MyCTRL.jhd (46, 2011-12-04)
myfpga\MCPU\MyCTRL.tbw (614, 2011-11-10)
myfpga\MCPU\MyGETIR.jhd (48, 2011-12-04)
myfpga\MCPU\MyGETIR.tbw (481, 2011-11-28)
myfpga\MCPU\MyMEM.jhd (44, 2011-12-04)
myfpga\MCPU\MyMEM.tbw (479, 2011-11-08)
myfpga\MCPU\xst\work\hdllib.ref (885, 2011-12-04)
myfpga\MCPU\xst\work\hdpdeps.ref (2270, 2011-12-04)
myfpga\MCPU\xst\work\sub00\vhpl00.vho (833, 2011-12-04)
myfpga\MCPU\xst\work\sub00\vhpl01.vho (2112, 2011-12-04)
myfpga\MCPU\xst\work\sub00\vhpl02.vho (1411, 2011-12-04)
myfpga\MCPU\xst\work\sub00\vhpl03.vho (1971, 2011-12-04)
... ...
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