111
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：32KB
下载次数：1
上传日期：2014-11-12 17:23:46
上 传 者：
linjiano
说明： FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）
(FPGA to achieve full-duplex asynchronous serial interface (UART), to communicate with the PC. A start bit 8 data bits one stop bit no parity bit 2400,4800,9600,11520 optional or variable baud rate (baud rate mode button control available))
文件列表:
vhdl\example\Chapter5 Sample\UART (0, 2006-11-11)
vhdl\example\Chapter5 Sample\UART\automake.log (0, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\baudrate_generator.jhd (27, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\baudrate_generator.vhd (1549, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\baudrate_generator_TB.jhd (63, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\baudrate_generator_TB.vhd (2796, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\counter.jhd (16, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\counter.vhd (926, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\counter_TB.jhd (41, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\counter_TB.vhd (2375, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\detector.jhd (17, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\detector.vhd (852, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\detector_TB.jhd (43, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\detector_TB.vhd (2474, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\parity_verifier.jhd (24, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\parity_verifier.vhd (704, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\parity_verifier_TB.jhd (57, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\parity_verifier_TB.vhd (2439, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\shift_register.jhd (23, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\shift_register.vhd (1070, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\shift_register_TB.jhd (55, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\shift_register_TB.vhd (2669, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch.jhd (15, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch.vhd (436, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch_bus.jhd (19, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch_bus.vhd (641, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch_bus_TB.jhd (47, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\switch_bus_TB.vhd (2463, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\UART.npl (1015, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_core.jhd (18, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_core.vhd (6584, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\UART_PACKAGE.vhd (1570, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_top.jhd (224, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_top.vhd (7511, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_top_tb.jhd (43, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\uart_top_tb.vhd (3156, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\__projnav (0, 2006-11-11)
vhdl\example\Chapter5 Sample\UART\__projnav.log (44820, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\__projnav\p00p5000.kis (618, 2005-04-12)
vhdl\example\Chapter5 Sample\UART\__projnav\p00pi000.kis (618, 2005-04-12)
... ...
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