jisuanqi
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5453KB
下载次数：15
上传日期：2014-11-29 19:00:23
上 传 者：
qingfeng123456
说明： fpga开发板实现按键两位数加减乘除运算。通过数码管显示
(FPGA development board to achieve key two digit add, subtract, multiply and divide operations. Through the digital tube display
)
文件列表:
jisuanqi\jisuanqi.qpf (1286, 2014-05-20)
jisuanqi\jisuanqi.qsf (7887, 2014-06-19)
jisuanqi\anjian.v (1982, 2014-05-20)
jisuanqi\anjian.v.bak (1963, 2014-05-20)
jisuanqi\display.v (420, 2014-05-20)
jisuanqi\sw.v (703, 2014-05-20)
jisuanqi\sw.v.bak (478, 2014-05-20)
jisuanqi\xuanze.v (658, 2014-05-20)
jisuanqi\display.v.bak (425, 2014-05-20)
jisuanqi\xuanze.v.bak (580, 2014-05-20)
jisuanqi\jisuan.v (1160, 2014-05-20)
jisuanqi\jisuan.v.bak (557, 2014-05-20)
jisuanqi\fa.v (304, 2014-05-20)
jisuanqi\les.v (546, 2014-05-20)
jisuanqi\top.v (2174, 2014-05-20)
jisuanqi\top.v.bak (451, 2014-05-20)
jisuanqi\fa.v.bak (304, 2014-05-20)
jisuanqi\jisuanqi.v (2192, 2014-05-20)
jisuanqi\jisuanqi.v.bak (2174, 2014-05-20)
jisuanqi\jisuanqi_nativelink_simulation.rpt (865, 2014-05-20)
jisuanqi\jisuanqi.qws (48, 2014-06-19)
jisuanqi\simulation\modelsim\jisuanqi_modelsim.xrf (163102, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_8l_1000mv_100c_slow.vo (1315239, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_8l_1000mv_-40c_slow.vo (1315239, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_min_1000mv_-40c_fast.vo (1315240, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi.vo (1315219, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_8l_1000mv_100c_v_slow.sdo (764174, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_8l_1000mv_-40c_v_slow.sdo (763235, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_min_1000mv_-40c_v_fast.sdo (768202, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_v.sdo (764174, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi.vt (2647, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi.vt.bak (3386, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi_run_msim_rtl_verilog.do (1122, 2014-05-20)
jisuanqi\simulation\modelsim\msim_transcript (3304, 2014-05-20)
jisuanqi\simulation\modelsim\modelsim.ini (11131, 2014-05-20)
jisuanqi\simulation\modelsim\vsim.wlf (90112, 2014-05-20)
jisuanqi\simulation\modelsim\jisuanqi.sft (374, 2014-05-20)
jisuanqi\simulation\modelsim\rtl_work\_info (3593, 2014-05-20)
jisuanqi\simulation\modelsim\rtl_work\_vmake (26, 2014-05-20)
jisuanqi\simulation\modelsim\rtl_work\jisuanqi_vlg_tst\_primary.vhd (92, 2014-05-20)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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