EDA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3541KB
下载次数：14
上传日期：2014-12-01 10:30:19
上 传 者：
wangqianqianLUT
说明： 采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台，采用自顶向下的模块化设计思想将整个IIR数字滤波器分为：时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后，进行了仿真和综合。
(IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ design platform, using a top-down modular design the entire IIR digital filter divided into: timing control, delay, complement multiply and accumulate four functional modules. Respectively, after each module using VHDL description, simulation and synthesis.)
文件列表:
EDA (0, 2014-04-15)
EDA\IRR1 (0, 2014-04-15)
EDA\IRR1\IRR1.bdf (15178, 2012-07-05)
EDA\IRR1\IRR1.flow.rpt (6564, 2012-07-06)
EDA\IRR1\IRR1.map.rpt (12638, 2012-07-06)
EDA\IRR1\IRR1.map.summary (657, 2012-07-06)
EDA\IRR1\IRR1.qpf (1258, 2012-07-05)
EDA\IRR1\IRR1.qsf (2962, 2012-07-06)
EDA\IRR1\IRR1.qws (2506, 2012-07-06)
EDA\IRR1\addyn.vhd (620, 2012-07-06)
EDA\IRR1\addyn.vhd.bak (620, 2012-07-06)
EDA\IRR1\control.vhd (777, 2012-07-06)
EDA\IRR1\control.vhd.bak (777, 2012-07-06)
EDA\IRR1\db (0, 2014-04-15)
EDA\IRR1\db\IRR1.cbx.xml (86, 2012-07-06)
EDA\IRR1\db\IRR1.cmp.rdb (3427, 2012-07-06)
EDA\IRR1\db\IRR1.db_info (137, 2012-07-05)
EDA\IRR1\db\IRR1.eco.cdb (161, 2012-07-06)
EDA\IRR1\db\IRR1.hif (248, 2012-07-06)
EDA\IRR1\db\IRR1.map.qmsg (7346, 2012-07-06)
EDA\IRR1\db\IRR1.map_bb.hdb (6156, 2012-07-06)
EDA\IRR1\db\IRR1.sld_design_entry.sci (154, 2012-07-06)
EDA\IRR1\db\IRR1.tis_db_list.ddb (174, 2012-07-06)
EDA\IRR1\db\prev_cmp_IRR1.map.qmsg (7346, 2012-07-06)
EDA\IRR1\db\prev_cmp_IRR1.qmsg (7584, 2012-07-06)
EDA\IRR1\delay.vhd (882, 2012-07-06)
EDA\IRR1\delay.vhd.bak (875, 2012-07-06)
EDA\IRR1\incremental_db (0, 2014-04-15)
EDA\IRR1\incremental_db\compiled_partitions (0, 2014-12-01)
EDA\IRR1\smultadd1.vhd (1582, 2012-07-06)
EDA\IRR1\smultadd1.vhd.bak (1582, 2012-07-06)
EDA\addyn (0, 2014-04-15)
EDA\addyn\addyn.asm.rpt (6948, 2012-07-06)
EDA\addyn\addyn.bdf (4058, 2012-07-07)
EDA\addyn\addyn.bsf (1972, 2012-07-07)
EDA\addyn\addyn.done (26, 2012-07-08)
EDA\addyn\addyn.fit.rpt (154028, 2012-07-06)
EDA\addyn\addyn.fit.smsg (513, 2012-07-06)
EDA\addyn\addyn.fit.summary (597, 2012-07-06)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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