second
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：455KB
下载次数：7
上传日期：2014-12-05 11:03:47
上 传 者：
马门dd
说明： 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计
(Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BCD/7 segment decoder IC 74LS47 simulation, single-tube type stable operating point voltage divider bias circuit simulation and 8 quiz Responder circuit design)
文件列表:
second\报告.doc (744960, 2014-12-05)
second (0, 2014-12-05)
second\LIB.DLS (41, 2013-12-03)
second\U2600752.DLS (27361, 2013-12-03)
second\watch(1).cnf (21003, 2013-11-30)
second\watch(10).cnf (2469, 2013-11-30)
second\watch(11).cnf (10957, 2013-11-30)
second\watch(12).cnf (6629, 2013-11-30)
second\watch(13).cnf (22584, 2013-11-30)
second\watch(14).cnf (2675, 2013-11-30)
second\watch(2).cnf (12881, 2013-11-30)
second\watch(3).cnf (22584, 2013-11-30)
second\watch(4).cnf (22584, 2013-11-30)
second\watch(5).cnf (4747, 2013-11-30)
second\watch(6).cnf (1851, 2013-11-30)
second\watch(7).cnf (9958, 2013-11-30)
second\watch(8).cnf (6319, 2013-11-30)
second\watch(9).cnf (22584, 2013-11-30)
second\watch.acf (15909, 2014-12-05)
second\watch.cnf (162035, 2013-12-03)
second\watch.fit (22558, 2014-12-05)
second\watch.hif (9442, 2014-12-05)
second\watch.jam (51551, 2014-12-05)
second\watch.jbc (44397, 2014-12-05)
second\watch.mmf (507, 2014-12-05)
second\watch.ndb (94899, 2014-12-05)
second\watch.pin (5170, 2014-12-05)
second\watch.pof (25322, 2014-12-05)
second\watch.rpt (72092, 2014-12-05)
second\watch.scf (64745, 2014-12-05)
second\watch.snf (175175, 2014-12-05)
second\watch.v (5074, 2013-12-03)
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