start_lab4
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：21669KB
下载次数：1
上传日期：2014-12-05 13:39:10
上 传 者：
hesen199155
说明： 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数
(
Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0)
文件列表:
start_lab4 (0, 2014-11-25)
start_lab4\db (0, 2014-11-25)
start_lab4\db\altsyncram_iss3.tdf (15926, 2014-10-29)
start_lab4\db\altsyncram_ups3.tdf (12706, 2014-10-29)
start_lab4\db\cmpr_efc.tdf (1682, 2014-10-29)
start_lab4\db\cmpr_gfc.tdf (1848, 2014-10-29)
start_lab4\db\cmpr_hfc.tdf (1914, 2014-10-29)
start_lab4\db\cntr_0fi.tdf (3731, 2014-10-29)
start_lab4\db\cntr_22j.tdf (3042, 2014-10-29)
start_lab4\db\cntr_5fi.tdf (3731, 2014-10-29)
start_lab4\db\cntr_95j.tdf (3564, 2014-10-29)
start_lab4\db\cntr_ldi.tdf (3599, 2014-10-29)
start_lab4\db\cntr_odi.tdf (3730, 2014-10-29)
start_lab4\db\cntr_p1j.tdf (3296, 2014-10-29)
start_lab4\db\dec_segment.(0).cnf.cdb (1319, 2014-11-03)
start_lab4\db\dec_segment.(0).cnf.hdb (737, 2014-11-03)
start_lab4\db\dec_segment.asm.qmsg (2208, 2014-11-03)
start_lab4\db\dec_segment.asm.rdb (1357, 2014-11-03)
start_lab4\db\dec_segment.asm_labs.ddb (9413, 2014-11-03)
start_lab4\db\dec_segment.cbx.xml (93, 2014-11-03)
start_lab4\db\dec_segment.cmp.bpm (558, 2014-11-03)
start_lab4\db\dec_segment.cmp.cdb (4131, 2014-11-03)
start_lab4\db\dec_segment.cmp.ecobp (28, 2014-11-03)
start_lab4\db\dec_segment.cmp.hdb (8569, 2014-11-03)
start_lab4\db\dec_segment.cmp.kpt (199, 2014-11-03)
start_lab4\db\dec_segment.cmp.logdb (11196, 2014-11-03)
start_lab4\db\dec_segment.cmp.rdb (19517, 2014-11-03)
start_lab4\db\dec_segment.cmp_merge.kpt (204, 2014-11-03)
start_lab4\db\dec_segment.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd (289707, 2014-11-03)
start_lab4\db\dec_segment.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd (286393, 2014-11-03)
start_lab4\db\dec_segment.db_info (136, 2014-11-03)
start_lab4\db\dec_segment.eco.cdb (160, 2014-11-03)
start_lab4\db\dec_segment.fit.qmsg (15272, 2014-11-03)
start_lab4\db\dec_segment.hier_info (519, 2014-11-03)
start_lab4\db\dec_segment.hif (771, 2014-11-03)
start_lab4\db\dec_segment.lpc.html (430, 2014-11-03)
start_lab4\db\dec_segment.lpc.rdb (384, 2014-11-03)
start_lab4\db\dec_segment.lpc.txt (1060, 2014-11-03)
start_lab4\db\dec_segment.map.bpm (553, 2014-11-03)
start_lab4\db\dec_segment.map.cdb (1447, 2014-11-03)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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