文件列表:

ST_NAND01GR3B_V30\cds.lib (67, 2006-10-18)
ST_NAND01GR3B_V30\code (0, 2006-10-18)
ST_NAND01GR3B_V30\code\NAND01GR3B.vhd (166026, 2006-10-18)
ST_NAND01GR3B_V30\doc (0, 2006-10-18)
ST_NAND01GR3B_V30\doc\NANDxxxxxBxx_UserManual.pdf (62724, 2006-10-18)
ST_NAND01GR3B_V30\hdl.var (100, 2006-10-18)
ST_NAND01GR3B_V30\lib (0, 2006-10-18)
ST_NAND01GR3B_V30\lib\BlockLib.vhd (6300, 2006-10-18)
ST_NAND01GR3B_V30\lib\CoreComponents.vhd (7479, 2006-10-18)
ST_NAND01GR3B_V30\lib\CUIcommandData.vhd (6678, 2006-10-18)
ST_NAND01GR3B_V30\lib\Data.vhd (18091, 2006-10-18)
ST_NAND01GR3B_V30\lib\MemoryLib.vhd (36209, 2006-10-18)
ST_NAND01GR3B_V30\lib\ResFunctions.vhd (8899, 2006-10-18)
ST_NAND01GR3B_V30\lib\StringLib.vhd (22513, 2006-10-18)
ST_NAND01GR3B_V30\lib\TimingData.vhd (10650, 2006-10-18)
ST_NAND01GR3B_V30\lib\UserData.vhd (1831, 2006-10-18)
ST_NAND01GR3B_V30\run_ncsim (3080, 2006-10-18)
ST_NAND01GR3B_V30\sim (0, 2006-10-18)
ST_NAND01GR3B_V30\stim (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\erase (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\erase\erase.vhd (10556, 2006-10-18)
ST_NAND01GR3B_V30\stim\lock (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\lock\BlockUnlock.vhd (10695, 2006-10-18)
ST_NAND01GR3B_V30\stim\lock\LockDown.vhd (11273, 2006-10-18)
ST_NAND01GR3B_V30\stim\others (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\others\reset.vhd (10426, 2006-10-18)
ST_NAND01GR3B_V30\stim\others\test_PRL.vhd (12458, 2006-10-18)
ST_NAND01GR3B_V30\stim\others\test_WPN.vhd (13054, 2006-10-18)
ST_NAND01GR3B_V30\stim\program (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\program\cache_program.vhd (13253, 2006-10-18)
ST_NAND01GR3B_V30\stim\program\copy_back.vhd (11899, 2006-10-18)
ST_NAND01GR3B_V30\stim\program\program.vhd (10279, 2006-10-18)
ST_NAND01GR3B_V30\stim\program\random_data_input.vhd (11043, 2006-10-18)
ST_NAND01GR3B_V30\stim\read (0, 2006-10-18)
ST_NAND01GR3B_V30\stim\read\cache_read.vhd (10435, 2006-10-18)
ST_NAND01GR3B_V30\stim\read\random_read.vhd (11736, 2006-10-18)
ST_NAND01GR3B_V30\stim\read\read_signature.vhd (9870, 2006-10-18)
ST_NAND01GR3B_V30\stim\read\read_SR.vhd (10966, 2006-10-18)
ST_NAND01GR3B_V30\top (0, 2006-10-18)
... ...

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ _/ _/ ____________________________________________ _/ _/ / / _/_/ _/ / NAND01GR3B / _/_/_/ _/ / / _/_/ _/ / 1Gbit / _/_/ _/ / 8 bit, 2112 Byte Page, 1.8 V, NAND / _/ _/ / / _/ _/ / VHDL Behavioral Model / _/ _/ / Version 3.0 / _/_/ _/ / / _/_/_/ _/ / Copyright (c) 2006 STMicroelectronics / _/_/_/ _/ /___________________________________________/ _/_/_/_/_/ _/ This README provides information on the following topics : - VHDL Behavioral Model description - Version History - Install / uninstall information - File list - Get support - Bug reports - Send feedback / requests for features - Known issues - Ordering information ------------------------------------ VHDL BEHAVIORAL MODEL DESCRIPTION ------------------------------------ Behavioral modeling is a technic for the description of an hardware architecture at an algorithmic level where the designers do not necessarily think in terms of logic gates or data flow, but in terms of the algorithm and its performance. Only after the high-level architecture and algorithm are finalized, do designers start focusing on building the digital circuit to implement the algorithm. To obtain this behavioral model we used VHDL Language. --------------- VERSION HISTORY --------------- Version 3.0 Date : 18/10/2006 Note : Bug fixed on cache program timing. Bug fixed on lock-down operation. New console output messages: - address latching with block number and page number indication; - output messages when WP_N and PRL signals changes; - indication of lock command result; - others improvements on output messages. Developed by : Aniello Viscardi Tel : +39 81 2381199 e-mail : aniello.viscardi@st.com This version is based on the Datasheet: NAND01G-B, NAND02G-B / Rev 4.0 / February 2006 Version 2.2 Date : 7/08/2006 Note : Fixed bug on isDebug option Developed by : Aniello Viscardi Tel : +39 81 2381199 e-mail : aniello.viscardi@st.com This version is based on the Datasheet: NAND01G-B, NAND02G-B / Rev 4.0 / February 2006 Version 2.1 Date : 27/07/2006 Note : WP_N signal followed by SR7 bit of status register Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com Aniello Viscardi Tel : +39 81 2381199 e-mail : aniello.viscardi@st.com This version is based on the Datasheet: NAND01G-B, NAND02G-B / Rev 4.0 / February 2006 Version 2.0 Date : 25/07/2006 Note : Cache read operation bug fixed (with the bug, in same conditions, first data readed was the same data of the previous read operation) Fixed bug relating tEHQZ warning Now console prompt block number with too, in address latch operation Optimize console prompt of "busy state" Improved modelling of lock-unlock operation, when PRL=0 Fixed address_latch bug relating spare area Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com Aniello Viscardi Tel : +39 81 2381199 e-mail : aniello.viscardi@st.com This version is based on the Datasheet: NAND01G-B, NAND02G-B / Rev 4.0 / February 2006 Version 1.5 Date : 22/06/2006 Note : bug fixed in Block Latch when a Block UnLock Operation is on going Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) Version 1.4 Date : 19/06/2006 Note : bug fixed in Block UnLock and Cache Read Operation. Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) Version 1.3 Date : 22/05/2006 Note : bug fixed in Latch Block Address. Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) Version 1.2 Date : 12/05/2006 Note : bug fixed in PRL signal and Block Lock operation. Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) Version 1.1 Date : 07/05/2006 Note : bug fixed in Block Address Latch. Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) Version 1.0 Date : 23/03/2006 Note : First Release Developed by : Giampaolo Giacopelli Tel : +39 91 6689948 e-mail : giampaolo.giacopelli@st.com This version is based on the Target Specification Datasheet (October 2004) --------------------------------- INSTALL / UNINSTALL INFORMATION --------------------------------- For installing the model you have to process the ST_NAND01GR3B_V30.zip delivery package. Compatibility: the model has been tested by Cadence NCsim 5.4 simulator, on SUN OS environment. IMPORTANT: ****************************************************************************** THIS PROGRAM IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. ****************************************************************************** -------------- FILE LIST -------------- code (source code files) - code/NANDxxxxxBxx.vhd lib (source library files) - lib/UserData.vhd - lib/Data.vhd - lib/CUIcommandData.vhd - lib/TimingData.vhd - lib/StringLib.vhd - lib/MemoryLib.vhd - lib/BlockLib.vhd - lib/CoreComponents.vhd - lib/ResFunctions.vhd doc (model documentation) - doc/ApplicationNote.pdf sim (files for simulation) - sim/memory_file - ./run_ncsim stim (stimuli files for simulation) - read/random_read.vhd - read/cache_read.vhd - read/read_signature.vhd - read/read_SR.vhd - lock/BlockUnlock.vhd - lock/LockDown.vhd - erase/erase.vhd - program/cache_program.vhd - program/program.vhd - program/random_data_input.vhd - program/copy_back.vhd - others/reset.vhd - others/test_PRL.vhd - others/test_WPN.vhd top (testbech file for simulation) - top/TestBench.vhd ------------- GET SUPPORT ------------- Please mail any questions, comments or problems you might have concerning this VHDL Behavioral Model to : giampaolo.giacopelli@st.com antonella.cavadi@st.com aniello.viscardi@st.com If you are having technical difficulties then please include some basic information in your email: Simulator Version and Operative System you have used; Memory (RAM); Free Disk Space on installation drive; ------------- BUG REPORTS ------------- If you experience something you think might be a bug in the VHDL Behavioral Model, please report it by sending a message to : giampaolo.giacopelli@st.com antonella.cavadi@st.com aniello.viscardi@st.com Describe what you did (if anything), what happened and what version of the Model you have. Please use the form below for bug reports: Error message : Memory (RAM) : Free Disk Space on installation drive : Simulator Version and Operative System you have used : Stimulus source file : Waveform Image file (gif or jpeg format) : --------------------------------------- SEND FEEDBACK / REQUESTS FOR FEATURES --------------------------------------- Please let us know how to improve the behavioral model giampaolo.giacopelli@st.com antonella.cavadi@st.com aniello.viscardi@st.com -------------- KNOWN ISSUES -------------- --------------- HOW TO REQUEST? --------------- http://www.st.com/stonline/products/families/memories/fl_nand/nand_fo.htm

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：