double_closed_loop
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：193KB
下载次数：57
上传日期：2014-12-19 14:05:05
上 传 者：
CKmingming
说明： 本程序是基于zynq_7000的FPGA的一个同步电机控制的平台，verilog语言
(based on zynq_7000 fpga-MOTOR CONTROL)
文件列表:
double_closed_loop (0, 2012-12-10)
double_closed_loop\c_source (0, 2012-12-10)
double_closed_loop\c_source\helloworld.c (3764, 2012-11-13)
double_closed_loop\ip_source (0, 2012-12-10)
double_closed_loop\ip_source\AD_read.v (7396, 2012-09-27)
double_closed_loop\ip_source\encoder.v (2570, 2012-04-08)
double_closed_loop\ip_source\get_speed.v (5378, 2012-04-22)
double_closed_loop\ip_source\init.v (5932, 2012-05-06)
double_closed_loop\ip_source\low_pass_filter_s6_cw_bb.v (547, 2012-09-29)
double_closed_loop\ip_source\motor_ctrl.v (23745, 2012-10-07)
double_closed_loop\ip_source\PID_calc.v (4503, 2012-05-13)
double_closed_loop\ip_source\pid_ctrlr_cw_bb.v (628, 2012-09-30)
double_closed_loop\ip_source\pwmModule.v (10370, 2012-09-28)
double_closed_loop\ip_source\pwm_Counter.v (3766, 2012-05-07)
double_closed_loop\ip_source\read_LTC1407A.v (6111, 2012-05-27)
double_closed_loop\ip_source\timer.v (1854, 2012-04-07)
double_closed_loop\ip_source\type_convert.v (3247, 2012-05-15)
double_closed_loop\ip_source\vspi.v (24347, 2012-05-05)
double_closed_loop\ngc_file (0, 2012-12-10)
double_closed_loop\ngc_file\addsb_11_0_3a5dfc4b6f09baa6.ngc (27866, 2012-09-27)
double_closed_loop\ngc_file\addsb_11_0_43c73dc0002c9063.ngc (56899, 2012-09-28)
double_closed_loop\ngc_file\addsb_11_0_4904f4145041c6d8.ngc (55292, 2012-09-28)
double_closed_loop\ngc_file\addsb_11_0_701e862c5fa0cc1a.ngc (53690, 2012-09-30)
double_closed_loop\ngc_file\addsb_11_0_7f9f56d07f9cc93c.ngc (53684, 2012-09-27)
double_closed_loop\ngc_file\addsb_11_0_a0b160debcb31581.ngc (27866, 2012-09-28)
double_closed_loop\ngc_file\addsb_11_0_ac4242219c6d34f8.ngc (26269, 2012-09-27)
double_closed_loop\ngc_file\low_pass_filter_s6_cw.ngc (42438, 2012-09-29)
double_closed_loop\ngc_file\mult_11_2_237b25632ab5a987.ngc (23895, 2012-09-28)
double_closed_loop\ngc_file\mult_11_2_6037a792e9e926b2.ngc (21473, 2012-09-28)
double_closed_loop\ngc_file\mult_11_2_725be05d239ff597.ngc (23894, 2012-09-27)
double_closed_loop\ngc_file\mult_11_2_c4c9451e44f29e54.ngc (24104, 2012-09-28)
double_closed_loop\ngc_file\pid_ctrlr_cw.ngc (106393, 2012-09-30)
double_closed_loop\ngc_file\xlpersistentdff.ngc (660, 2012-09-29)
double_closed_loop\zedboard_RevC_v2.xml (14373, 2012-10-17)
zedboard_RevC_v2是本实验的配置文件，c_source是本实验软件工程的源代码，ip_source是本实验添加的ip核的源代码，ngc_file是生成时需要调用的网表
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